492a493,495
> def isVecPredReg(self):
> return 0
>
798,799c801
< warn_once("Vectors not supported yet in tracedata");
< /*traceData->setData(final_val);*/
---
> traceData->setData(tmp_d%d);
801c803
< '''
---
> ''' % self.dest_reg_idx
862a865,946
> class VecPredRegOperand(Operand):
> reg_class = 'VecPredRegClass'
>
> def __init__(self, parser, full_name, ext, is_src, is_dest):
> Operand.__init__(self, parser, full_name, ext, is_src, is_dest)
> self.parser = parser
>
> def isReg(self):
> return 1
>
> def isVecPredReg(self):
> return 1
>
> def makeDecl(self):
> return ''
>
> def makeConstructor(self, predRead, predWrite):
> c_src = ''
> c_dest = ''
>
> if self.is_src:
> c_src = src_reg_constructor % (self.reg_class, self.reg_spec)
>
> if self.is_dest:
> c_dest = dst_reg_constructor % (self.reg_class, self.reg_spec)
> c_dest += '\n\t_numVecPredDestRegs++;'
>
> return c_src + c_dest
>
> def makeRead(self, predRead):
> func = 'readVecPredRegOperand'
> if self.read_code != None:
> return self.buildReadCode(func)
>
> if predRead:
> rindex = '_sourceIndex++'
> else:
> rindex = '%d' % self.src_reg_idx
>
> c_read = '\t\t%s& tmp_s%s = xc->%s(this, %s);\n' % (
> 'const TheISA::VecPredRegContainer', rindex, func, rindex)
> if self.ext:
> c_read += '\t\tauto %s = tmp_s%s.as<%s>();\n' % (
> self.base_name, rindex,
> self.parser.operandTypeMap[self.ext])
> return c_read
>
> def makeReadW(self, predWrite):
> func = 'getWritableVecPredRegOperand'
> if self.read_code != None:
> return self.buildReadCode(func)
>
> if predWrite:
> rindex = '_destIndex++'
> else:
> rindex = '%d' % self.dest_reg_idx
>
> c_readw = '\t\t%s& tmp_d%s = xc->%s(this, %s);\n' % (
> 'TheISA::VecPredRegContainer', rindex, func, rindex)
> if self.ext:
> c_readw += '\t\tauto %s = tmp_d%s.as<%s>();\n' % (
> self.base_name, rindex,
> self.parser.operandTypeMap[self.ext])
> return c_readw
>
> def makeWrite(self, predWrite):
> func = 'setVecPredRegOperand'
> if self.write_code != None:
> return self.buildWriteCode(func)
>
> wb = '''
> if (traceData) {
> traceData->setData(tmp_d%d);
> }
> ''' % self.dest_reg_idx
> return wb
>
> def finalize(self, predRead, predWrite):
> super(VecPredRegOperand, self).finalize(predRead, predWrite)
> if self.is_dest:
> self.op_rd = self.makeReadW(predWrite) + self.op_rd
>
1115a1200
> self.numVecPredDestRegs = 0
1138a1224,1225
> elif op_desc.isVecPredReg():
> self.numVecPredDestRegs += 1
1346a1434
> header += '\n\t_numVecPredDestRegs = 0;'