1# Copyright (c) 2014, 2016, 2019 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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485 return 0
486
487 def isVecReg(self):
488 return 0
489
490 def isVecElem(self):
491 return 0
492
493 def isPCState(self):
494 return 0
495
496 def isPCPart(self):
497 return self.isPCState() and self.reg_spec
498
499 def hasReadPred(self):
500 return self.read_predicate != None

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790
791 def makeWrite(self, predWrite):
792 func = 'setVecRegOperand'
793 if self.write_code != None:
794 return self.buildWriteCode(func)
795
796 wb = '''
797 if (traceData) {
798 warn_once("Vectors not supported yet in tracedata");
799 /*traceData->setData(final_val);*/
800 }
801 '''
802 return wb
803
804 def finalize(self, predRead, predWrite):
805 super(VecRegOperand, self).finalize(predRead, predWrite)
806 if self.is_dest:
807 self.op_rd = self.makeReadW(predWrite) + self.op_rd
808
809class VecElemOperand(Operand):

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855 else:
856 c_write = self.base_name
857
858 c_write = ('\n\txc->setVecElemOperand(this, %d, %s);' %
859 (self.dest_reg_idx, c_write))
860
861 return c_write
862
863class CCRegOperand(Operand):
864 reg_class = 'CCRegClass'
865
866 def isReg(self):
867 return 1
868
869 def isCCReg(self):
870 return 1

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1108 self.sort()
1109 # enumerate source & dest register operands... used in building
1110 # constructor later
1111 self.numSrcRegs = 0
1112 self.numDestRegs = 0
1113 self.numFPDestRegs = 0
1114 self.numIntDestRegs = 0
1115 self.numVecDestRegs = 0
1116 self.numCCDestRegs = 0
1117 self.numMiscDestRegs = 0
1118 self.memOperand = None
1119
1120 # Flags to keep track if one or more operands are to be read/written
1121 # conditionally.
1122 self.predRead = False
1123 self.predWrite = False

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1131 op_desc.dest_reg_idx = self.numDestRegs
1132 self.numDestRegs += 1
1133 if op_desc.isFloatReg():
1134 self.numFPDestRegs += 1
1135 elif op_desc.isIntReg():
1136 self.numIntDestRegs += 1
1137 elif op_desc.isVecReg():
1138 self.numVecDestRegs += 1
1139 elif op_desc.isCCReg():
1140 self.numCCDestRegs += 1
1141 elif op_desc.isControlReg():
1142 self.numMiscDestRegs += 1
1143 elif op_desc.isMem():
1144 if self.memOperand:
1145 error("Code block has more than one memory operand.")
1146 self.memOperand = op_desc

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1339 # The header of the constructor declares the variables to be used
1340 # in the body of the constructor.
1341 header = ''
1342 header += '\n\t_numSrcRegs = 0;'
1343 header += '\n\t_numDestRegs = 0;'
1344 header += '\n\t_numFPDestRegs = 0;'
1345 header += '\n\t_numVecDestRegs = 0;'
1346 header += '\n\t_numVecElemDestRegs = 0;'
1347 header += '\n\t_numIntDestRegs = 0;'
1348 header += '\n\t_numCCDestRegs = 0;'
1349
1350 self.constructor = header + \
1351 self.operands.concatAttrStrings('constructor')
1352
1353 self.flags = self.operands.concatAttrLists('flags')
1354

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