1# Copyright (c) 2014 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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515 my_flags += self.flags[2]
516 return my_flags
517
518 def makeDecl(self):
519 # Note that initializations in the declarations are solely
520 # to avoid 'uninitialized variable' errors from the compiler.
521 return self.ctype + ' ' + self.base_name + ' = 0;\n';
522
523class IntRegOperand(Operand):
524 def isReg(self):
525 return 1
526
527 def isIntReg(self):
528 return 1
529
530 def makeConstructor(self, predRead, predWrite):
531 c_src = ''
532 c_dest = ''
533
534 if self.is_src:
535 c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s;' % (self.reg_spec)
536 if self.hasReadPred():
537 c_src = '\n\tif (%s) {%s\n\t}' % \
538 (self.read_predicate, c_src)
539
540 if self.is_dest:
541 c_dest = '\n\t_destRegIdx[_numDestRegs++] = %s;' % \
542 (self.reg_spec)
543 c_dest += '\n\t_numIntDestRegs++;'
544 if self.hasWritePred():
545 c_dest = '\n\tif (%s) {%s\n\t}' % \
546 (self.write_predicate, c_dest)
547
548 return c_src + c_dest
549
550 def makeRead(self, predRead):

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587 %s final_val = %s;
588 xc->setIntRegOperand(this, %s, final_val);\n
589 if (traceData) { traceData->setData(final_val); }
590 }''' % (wcond, self.ctype, self.base_name, windex)
591
592 return wb
593
594class FloatRegOperand(Operand):
595 def isReg(self):
596 return 1
597
598 def isFloatReg(self):
599 return 1
600
601 def makeConstructor(self, predRead, predWrite):
602 c_src = ''
603 c_dest = ''
604
605 if self.is_src:
606 c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Reg_Base;' % \
607 (self.reg_spec)
608
609 if self.is_dest:
610 c_dest = \
611 '\n\t_destRegIdx[_numDestRegs++] = %s + FP_Reg_Base;' % \
612 (self.reg_spec)
613 c_dest += '\n\t_numFPDestRegs++;'
614
615 return c_src + c_dest
616
617 def makeRead(self, predRead):
618 bit_select = 0
619 if (self.ctype == 'float' or self.ctype == 'double'):
620 func = 'readFloatRegOperand'

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649 {
650 %s final_val = %s;
651 %s\n
652 if (traceData) { traceData->setData(final_val); }
653 }''' % (self.ctype, self.base_name, wp)
654 return wb
655
656class CCRegOperand(Operand):
657 def isReg(self):
658 return 1
659
660 def isCCReg(self):
661 return 1
662
663 def makeConstructor(self, predRead, predWrite):
664 c_src = ''
665 c_dest = ''
666
667 if self.is_src:
668 c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + CC_Reg_Base;' % \
669 (self.reg_spec)
670 if self.hasReadPred():
671 c_src = '\n\tif (%s) {%s\n\t}' % \
672 (self.read_predicate, c_src)
673
674 if self.is_dest:
675 c_dest = \
676 '\n\t_destRegIdx[_numDestRegs++] = %s + CC_Reg_Base;' % \
677 (self.reg_spec)
678 c_dest += '\n\t_numCCDestRegs++;'
679 if self.hasWritePred():
680 c_dest = '\n\tif (%s) {%s\n\t}' % \
681 (self.write_predicate, c_dest)
682
683 return c_src + c_dest
684
685 def makeRead(self, predRead):

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722 %s final_val = %s;
723 xc->setCCRegOperand(this, %s, final_val);\n
724 if (traceData) { traceData->setData(final_val); }
725 }''' % (wcond, self.ctype, self.base_name, windex)
726
727 return wb
728
729class ControlRegOperand(Operand):
730 def isReg(self):
731 return 1
732
733 def isControlReg(self):
734 return 1
735
736 def makeConstructor(self, predRead, predWrite):
737 c_src = ''
738 c_dest = ''
739
740 if self.is_src:
741 c_src = \
742 '\n\t_srcRegIdx[_numSrcRegs++] = %s + Misc_Reg_Base;' % \
743 (self.reg_spec)
744
745 if self.is_dest:
746 c_dest = \
747 '\n\t_destRegIdx[_numDestRegs++] = %s + Misc_Reg_Base;' % \
748 (self.reg_spec)
749
750 return c_src + c_dest
751
752 def makeRead(self, predRead):
753 bit_select = 0
754 if (self.ctype == 'float' or self.ctype == 'double'):
755 error('Attempt to read control register as FP')
756 if self.read_code != None:

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