1# Copyright (c) 2014 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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510 return 0
511
512 def isIntReg(self):
513 return 0
514
515 def isCCReg(self):
516 return 0
517
518 def isControlReg(self):
519 return 0
520
521 def isPCState(self):
522 return 0
523
524 def isPCPart(self):
525 return self.isPCState() and self.reg_spec

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746 {
747 %s final_val = %s;
748 xc->setCCRegOperand(this, %s, final_val);\n
749 if (traceData) { traceData->setData(final_val); }
750 }''' % (wcond, self.ctype, self.base_name, windex)
751
752 return wb
753
754class ControlRegOperand(Operand):
755 def isReg(self):
756 return 1
757
758 def isControlReg(self):
759 return 1
760
761 def makeConstructor(self, predRead, predWrite):

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813
814 def makeConstructor(self, predRead, predWrite):
815 return ''
816
817 def makeDecl(self):
818 # Note that initializations in the declarations are solely
819 # to avoid 'uninitialized variable' errors from the compiler.
820 # Declare memory data variable.
821 return '%s %s = 0;\n' % (self.ctype, self.base_name)
822
823 def makeRead(self, predRead):
824 if self.read_code != None:
825 return self.buildReadCode()
826 return ''
827
828 def makeWrite(self, predWrite):
829 if self.write_code != None:

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904 self.sort()
905 # enumerate source & dest register operands... used in building
906 # constructor later
907 self.numSrcRegs = 0
908 self.numDestRegs = 0
909 self.numFPDestRegs = 0
910 self.numIntDestRegs = 0
911 self.numCCDestRegs = 0
912 self.numMiscDestRegs = 0
913 self.memOperand = None
914
915 # Flags to keep track if one or more operands are to be read/written
916 # conditionally.
917 self.predRead = False
918 self.predWrite = False
919

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926 op_desc.dest_reg_idx = self.numDestRegs
927 self.numDestRegs += 1
928 if op_desc.isFloatReg():
929 self.numFPDestRegs += 1
930 elif op_desc.isIntReg():
931 self.numIntDestRegs += 1
932 elif op_desc.isCCReg():
933 self.numCCDestRegs += 1
934 elif op_desc.isControlReg():
935 self.numMiscDestRegs += 1
936 elif op_desc.isMem():
937 if self.memOperand:
938 error("Code block has more than one memory operand.")
939 self.memOperand = op_desc
940
941 # Check if this operand has read/write predication. If true, then

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1122 # The header of the constructor declares the variables to be used
1123 # in the body of the constructor.
1124 header = ''
1125 header += '\n\t_numSrcRegs = 0;'
1126 header += '\n\t_numDestRegs = 0;'
1127 header += '\n\t_numFPDestRegs = 0;'
1128 header += '\n\t_numIntDestRegs = 0;'
1129 header += '\n\t_numCCDestRegs = 0;'
1130
1131 self.constructor = header + \
1132 self.operands.concatAttrStrings('constructor')
1133
1134 self.flags = self.operands.concatAttrLists('flags')
1135
1136 self.op_class = None
1137

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2287 self.operandNameMap = operand_name
2288
2289 # Define operand variables.
2290 operands = user_dict.keys()
2291 extensions = self.operandTypeMap.keys()
2292
2293 operandsREString = r'''
2294 (?<!\w) # neg. lookbehind assertion: prevent partial matches
2295 ((%s)(?:_(%s))?) # match: operand with optional '_' then suffix
2296 (?!\w) # neg. lookahead assertion: prevent partial matches
2297 ''' % (string.join(operands, '|'), string.join(extensions, '|'))
2298
2299 self.operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE)
2300
2301 # Same as operandsREString, but extension is mandatory, and only two
2302 # groups are returned (base and ext, not full name as above).
2303 # Used for subtituting '_' for '.' to make C++ identifiers.

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