mem.cc (11308:7d8836fd043d) mem.cc (11692:e772fdcd3809)
1/*
2 * Copyright (c) 2012-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Author: Steve Reinhardt
34 */
35
36#include "arch/hsail/insts/mem.hh"
37
38#include "arch/hsail/Brig.h"
1/*
2 * Copyright (c) 2012-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 22 unchanged lines hidden (view full) ---

31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Author: Steve Reinhardt
34 */
35
36#include "arch/hsail/insts/mem.hh"
37
38#include "arch/hsail/Brig.h"
39#include "enums/OpType.hh"
40
41using namespace Brig;
42
43namespace HsailISA
44{
45 const char* atomicOpToString(BrigAtomicOperation brigOp);
46
39
40using namespace Brig;
41
42namespace HsailISA
43{
44 const char* atomicOpToString(BrigAtomicOperation brigOp);
45
47 Enums::MemOpType
48 brigAtomicToMemOpType(BrigOpcode brigOpCode, BrigAtomicOperation brigOp)
49 {
50 if (brigOpCode == Brig::BRIG_OPCODE_ATOMIC) {
51 switch (brigOp) {
52 case BRIG_ATOMIC_AND:
53 return Enums::MO_AAND;
54 case BRIG_ATOMIC_OR:
55 return Enums::MO_AOR;
56 case BRIG_ATOMIC_XOR:
57 return Enums::MO_AXOR;
58 case BRIG_ATOMIC_CAS:
59 return Enums::MO_ACAS;
60 case BRIG_ATOMIC_EXCH:
61 return Enums::MO_AEXCH;
62 case BRIG_ATOMIC_ADD:
63 return Enums::MO_AADD;
64 case BRIG_ATOMIC_WRAPINC:
65 return Enums::MO_AINC;
66 case BRIG_ATOMIC_WRAPDEC:
67 return Enums::MO_ADEC;
68 case BRIG_ATOMIC_MIN:
69 return Enums::MO_AMIN;
70 case BRIG_ATOMIC_MAX:
71 return Enums::MO_AMAX;
72 case BRIG_ATOMIC_SUB:
73 return Enums::MO_ASUB;
74 default:
75 fatal("Bad BrigAtomicOperation code %d\n", brigOp);
76 }
77 } else if (brigOpCode == Brig::BRIG_OPCODE_ATOMICNORET) {
78 switch (brigOp) {
79 case BRIG_ATOMIC_AND:
80 return Enums::MO_ANRAND;
81 case BRIG_ATOMIC_OR:
82 return Enums::MO_ANROR;
83 case BRIG_ATOMIC_XOR:
84 return Enums::MO_ANRXOR;
85 case BRIG_ATOMIC_CAS:
86 return Enums::MO_ANRCAS;
87 case BRIG_ATOMIC_EXCH:
88 return Enums::MO_ANREXCH;
89 case BRIG_ATOMIC_ADD:
90 return Enums::MO_ANRADD;
91 case BRIG_ATOMIC_WRAPINC:
92 return Enums::MO_ANRINC;
93 case BRIG_ATOMIC_WRAPDEC:
94 return Enums::MO_ANRDEC;
95 case BRIG_ATOMIC_MIN:
96 return Enums::MO_ANRMIN;
97 case BRIG_ATOMIC_MAX:
98 return Enums::MO_ANRMAX;
99 case BRIG_ATOMIC_SUB:
100 return Enums::MO_ANRSUB;
101 default:
102 fatal("Bad BrigAtomicOperation code %d\n", brigOp);
103 }
104 } else {
105 fatal("Bad BrigAtomicOpcode %d\n", brigOpCode);
106 }
107 }
108
109 const char*
110 atomicOpToString(BrigAtomicOperation brigOp)
111 {
112 switch (brigOp) {
113 case BRIG_ATOMIC_AND:
114 return "and";
115 case BRIG_ATOMIC_OR:
116 return "or";

--- 23 unchanged lines hidden --- 		46 const char*
47 atomicOpToString(BrigAtomicOperation brigOp)
48 {
49 switch (brigOp) {
50 case BRIG_ATOMIC_AND:
51 return "and";
52 case BRIG_ATOMIC_OR:
53 return "or";

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