1/* 2 * Copyright (c) 2012-2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: --- 117 unchanged lines hidden (view full) --- 126 } 127 } 128 129 void 130 Ret::execute(GPUDynInstPtr gpuDynInst) 131 { 132 Wavefront *w = gpuDynInst->wavefront(); 133 |
134 const VectorMask &mask = w->getPred(); |
135 136 // mask off completed work-items 137 for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) { 138 if (mask[lane]) { |
139 w->initMask[lane] = 0; |
140 } 141 142 } 143 144 // delete extra instructions fetched for completed work-items 145 w->instructionBuffer.erase(w->instructionBuffer.begin() + 1, 146 w->instructionBuffer.end()); 147 if (w->pendingFetch) { 148 w->dropFetch = true; 149 } 150 151 // if all work-items have completed, then wave-front is done |
152 if (w->initMask.none()) { |
153 w->status = Wavefront::S_STOPPED; 154 155 int32_t refCount = w->computeUnit->getLds(). |
156 decreaseRefCounter(w->dispatchId, w->wgId); |
157 158 DPRINTF(GPUExec, "CU%d: decrease ref ctr WG[%d] to [%d]\n", |
159 w->computeUnit->cu_id, w->wgId, refCount); |
160 161 // free the vector registers of the completed wavefront 162 w->computeUnit->vectorRegsReserved[w->simdId] -= 163 w->reservedVectorRegs; 164 165 assert(w->computeUnit->vectorRegsReserved[w->simdId] >= 0); 166 167 uint32_t endIndex = (w->startVgprIndex + --- 28 unchanged lines hidden (view full) --- 196 } 197 } 198 199 void 200 Barrier::execute(GPUDynInstPtr gpuDynInst) 201 { 202 Wavefront *w = gpuDynInst->wavefront(); 203 |
204 assert(w->barrierCnt == w->oldBarrierCnt); 205 w->barrierCnt = w->oldBarrierCnt + 1; |
206 w->stalledAtBarrier = true; 207 } 208} // namespace HsailISA |