branch.hh (11534:7106f550afad) branch.hh (11692:e772fdcd3809)
1/*
2 * Copyright (c) 2012-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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54 void generateDisassembly() override;
55
56 Brig::BrigWidth8_t width;
57 TargetType target;
58
59 BrnInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
60 : HsailGPUStaticInst(obj, "brn")
61 {
1/*
2 * Copyright (c) 2012-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 45 unchanged lines hidden (view full) ---

54 void generateDisassembly() override;
55
56 Brig::BrigWidth8_t width;
57 TargetType target;
58
59 BrnInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
60 : HsailGPUStaticInst(obj, "brn")
61 {
62 o_type = Enums::OT_BRANCH;
62 setFlag(Branch);
63 setFlag(UnconditionalJump);
63 width = ((Brig::BrigInstBr*)ib)->width;
64 unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
65 target.init(op_offs, obj);
64 width = ((Brig::BrigInstBr*)ib)->width;
65 unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
66 target.init(op_offs, obj);
66 o_type = Enums::OT_BRANCH;
67 }
68
69 uint32_t getTargetPc() override { return target.getTarget(0, 0); }
70
67 }
68
69 uint32_t getTargetPc() override { return target.getTarget(0, 0); }
70
71 bool unconditionalJumpInstruction() override { return true; }
72 bool isVectorRegister(int operandIndex) override {
73 assert(operandIndex >= 0 && operandIndex < getNumOperands());
74 return target.isVectorRegister();
75 }
76 bool isCondRegister(int operandIndex) override {
77 assert(operandIndex >= 0 && operandIndex < getNumOperands());
78 return target.isCondRegister();
79 }

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170
171 Brig::BrigWidth8_t width;
172 CRegOperand cond;
173 TargetType target;
174
175 CbrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
176 : HsailGPUStaticInst(obj, "cbr")
177 {
71 bool isVectorRegister(int operandIndex) override {
72 assert(operandIndex >= 0 && operandIndex < getNumOperands());
73 return target.isVectorRegister();
74 }
75 bool isCondRegister(int operandIndex) override {
76 assert(operandIndex >= 0 && operandIndex < getNumOperands());
77 return target.isCondRegister();
78 }

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169
170 Brig::BrigWidth8_t width;
171 CRegOperand cond;
172 TargetType target;
173
174 CbrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
175 : HsailGPUStaticInst(obj, "cbr")
176 {
178 o_type = Enums::OT_BRANCH;
177 setFlag(Branch);
179 width = ((Brig::BrigInstBr *)ib)->width;
180 unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
181 cond.init(op_offs, obj);
182 op_offs = obj->getOperandPtr(ib->operands, 1);
183 target.init(op_offs, obj);
178 width = ((Brig::BrigInstBr *)ib)->width;
179 unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
180 cond.init(op_offs, obj);
181 op_offs = obj->getOperandPtr(ib->operands, 1);
182 target.init(op_offs, obj);
184 o_type = Enums::OT_BRANCH;
185 }
186
187 uint32_t getTargetPc() override { return target.getTarget(0, 0); }
188
189 void execute(GPUDynInstPtr gpuDynInst) override;
190 // Assumption: Target is operand 0, Condition Register is operand 1
191 bool isVectorRegister(int operandIndex) override {
192 assert(operandIndex >= 0 && operandIndex < getNumOperands());

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338 void generateDisassembly() override;
339
340 ImmOperand<uint32_t> width;
341 TargetType target;
342
343 BrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
344 : HsailGPUStaticInst(obj, "br")
345 {
183 }
184
185 uint32_t getTargetPc() override { return target.getTarget(0, 0); }
186
187 void execute(GPUDynInstPtr gpuDynInst) override;
188 // Assumption: Target is operand 0, Condition Register is operand 1
189 bool isVectorRegister(int operandIndex) override {
190 assert(operandIndex >= 0 && operandIndex < getNumOperands());

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336 void generateDisassembly() override;
337
338 ImmOperand<uint32_t> width;
339 TargetType target;
340
341 BrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
342 : HsailGPUStaticInst(obj, "br")
343 {
346 o_type = Enums::OT_BRANCH;
344 setFlag(Branch);
345 setFlag(UnconditionalJump);
347 width.init(((Brig::BrigInstBr *)ib)->width, obj);
348 unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
349 target.init(op_offs, obj);
346 width.init(((Brig::BrigInstBr *)ib)->width, obj);
347 unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
348 target.init(op_offs, obj);
350 o_type = Enums::OT_BRANCH;
351 }
352
353 uint32_t getTargetPc() override { return target.getTarget(0, 0); }
354
349 }
350
351 uint32_t getTargetPc() override { return target.getTarget(0, 0); }
352
355 bool unconditionalJumpInstruction() override { return true; }
356
357 void execute(GPUDynInstPtr gpuDynInst) override;
358 bool isVectorRegister(int operandIndex) override {
359 assert(operandIndex >= 0 && operandIndex < getNumOperands());
360 return target.isVectorRegister();
361 }
362 bool isCondRegister(int operandIndex) override {
363 assert(operandIndex >= 0 && operandIndex < getNumOperands());
364 return target.isCondRegister();

--- 78 unchanged lines hidden --- 		353 void execute(GPUDynInstPtr gpuDynInst) override;
354 bool isVectorRegister(int operandIndex) override {
355 assert(operandIndex >= 0 && operandIndex < getNumOperands());
356 return target.isVectorRegister();
357 }
358 bool isCondRegister(int operandIndex) override {
359 assert(operandIndex >= 0 && operandIndex < getNumOperands());
360 return target.isCondRegister();

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