Cross Reference: /gem5/src/arch/hsail/insts/branch.hh

1/*
2 * Copyright (c) 2012-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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46
47 // The main difference between a direct branch and an indirect branch
48 // is whether the target is a register or a label, so we can share a
49 // lot of code if we template the base implementation on that type.
50 template<typename TargetType>
51 class BrnInstBase : public HsailGPUStaticInst
52 {
53 public:

54 void generateDisassembly();

54 void generateDisassembly() override;

55
56 Brig::BrigWidth8_t width;
57 TargetType target;
58
59 BrnInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
60 : HsailGPUStaticInst(obj, "brn")
61 {
62 o_type = Enums::OT_BRANCH;
63 width = ((Brig::BrigInstBr*)ib)->width;
64 unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
65 target.init(op_offs, obj);
66 o_type = Enums::OT_BRANCH;
67 }
68
69 uint32_t getTargetPc() override { return target.getTarget(0, 0); }
70
71 bool unconditionalJumpInstruction() override { return true; }

72 bool isVectorRegister(int operandIndex) {

72 bool isVectorRegister(int operandIndex) override {

73 assert(operandIndex >= 0 && operandIndex < getNumOperands());
74 return target.isVectorRegister();
75 }

76 bool isCondRegister(int operandIndex) {

76 bool isCondRegister(int operandIndex) override {

77 assert(operandIndex >= 0 && operandIndex < getNumOperands());
78 return target.isCondRegister();
79 }

80 bool isScalarRegister(int operandIndex) {

80 bool isScalarRegister(int operandIndex) override {

81 assert(operandIndex >= 0 && operandIndex < getNumOperands());
82 return target.isScalarRegister();
83 }
84

85 bool isSrcOperand(int operandIndex) {

85 bool isSrcOperand(int operandIndex) override {

86 assert(operandIndex >= 0 && operandIndex < getNumOperands());
87 return true;
88 }
89

90 bool isDstOperand(int operandIndex) {

90 bool isDstOperand(int operandIndex) override {

91 return false;
92 }
93

94 int getOperandSize(int operandIndex) {

94 int getOperandSize(int operandIndex) override {

95 assert(operandIndex >= 0 && operandIndex < getNumOperands());
96 return target.opSize();
97 }
98

99 int getRegisterIndex(int operandIndex) {

99 int getRegisterIndex(int operandIndex) override {

100 assert(operandIndex >= 0 && operandIndex < getNumOperands());
101 return target.regIndex();
102 }
103

104 int getNumOperands() {

104 int getNumOperands() override {

105 return 1;
106 }
107

108 void execute(GPUDynInstPtr gpuDynInst);

108 void execute(GPUDynInstPtr gpuDynInst) override;

109 };
110
111 template<typename TargetType>
112 void
113 BrnInstBase<TargetType>::generateDisassembly()
114 {
115 std::string widthClause;
116

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161
162 GPUStaticInst* decodeBrn(const Brig::BrigInstBase *ib,
163 const BrigObject *obj);
164
165 template<typename TargetType>
166 class CbrInstBase : public HsailGPUStaticInst
167 {
168 public:

169 void generateDisassembly();

169 void generateDisassembly() override;

170
171 Brig::BrigWidth8_t width;
172 CRegOperand cond;
173 TargetType target;
174
175 CbrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
176 : HsailGPUStaticInst(obj, "cbr")
177 {
178 o_type = Enums::OT_BRANCH;
179 width = ((Brig::BrigInstBr *)ib)->width;
180 unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
181 cond.init(op_offs, obj);
182 op_offs = obj->getOperandPtr(ib->operands, 1);
183 target.init(op_offs, obj);
184 o_type = Enums::OT_BRANCH;
185 }
186
187 uint32_t getTargetPc() override { return target.getTarget(0, 0); }
188

189 void execute(GPUDynInstPtr gpuDynInst);

189 void execute(GPUDynInstPtr gpuDynInst) override;

190 // Assumption: Target is operand 0, Condition Register is operand 1

191 bool isVectorRegister(int operandIndex) {

191 bool isVectorRegister(int operandIndex) override {

192 assert(operandIndex >= 0 && operandIndex < getNumOperands());
193 if (!operandIndex)
194 return target.isVectorRegister();
195 else
196 return false;
197 }

198 bool isCondRegister(int operandIndex) {

198 bool isCondRegister(int operandIndex) override {

199 assert(operandIndex >= 0 && operandIndex < getNumOperands());
200 if (!operandIndex)
201 return target.isCondRegister();
202 else
203 return true;
204 }

205 bool isScalarRegister(int operandIndex) {

205 bool isScalarRegister(int operandIndex) override {

206 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
207 if (!operandIndex)
208 return target.isScalarRegister();
209 else
210 return false;
211 }

212 bool isSrcOperand(int operandIndex) {

212 bool isSrcOperand(int operandIndex) override {

213 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
214 if (operandIndex == 0)
215 return true;
216 return false;
217 }
218 // both Condition Register and Target are source operands

219 bool isDstOperand(int operandIndex) {

219 bool isDstOperand(int operandIndex) override {

220 return false;
221 }

222 int getOperandSize(int operandIndex) {

222 int getOperandSize(int operandIndex) override {

223 assert(operandIndex >= 0 && operandIndex < getNumOperands());
224 if (!operandIndex)
225 return target.opSize();
226 else
227 return 1;
228 }

229 int getRegisterIndex(int operandIndex) {

229 int getRegisterIndex(int operandIndex) override {

230 assert(operandIndex >= 0 && operandIndex < getNumOperands());
231 if (!operandIndex)
232 return target.regIndex();
233 else
234 return -1;
235 }
236
237 // Operands = Target, Condition Register

238 int getNumOperands() {

238 int getNumOperands() override {

239 return 2;
240 }
241 };
242
243 template<typename TargetType>
244 void
245 CbrInstBase<TargetType>::generateDisassembly()
246 {

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330
331 GPUStaticInst* decodeCbr(const Brig::BrigInstBase *ib,
332 const BrigObject *obj);
333
334 template<typename TargetType>
335 class BrInstBase : public HsailGPUStaticInst
336 {
337 public:

338 void generateDisassembly();

338 void generateDisassembly() override;

339
340 ImmOperand<uint32_t> width;
341 TargetType target;
342
343 BrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
344 : HsailGPUStaticInst(obj, "br")
345 {
346 o_type = Enums::OT_BRANCH;
347 width.init(((Brig::BrigInstBr *)ib)->width, obj);
348 unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
349 target.init(op_offs, obj);
350 o_type = Enums::OT_BRANCH;
351 }
352
353 uint32_t getTargetPc() override { return target.getTarget(0, 0); }
354
355 bool unconditionalJumpInstruction() override { return true; }
356

357 void execute(GPUDynInstPtr gpuDynInst);
358 bool isVectorRegister(int operandIndex) {

357 void execute(GPUDynInstPtr gpuDynInst) override;
358 bool isVectorRegister(int operandIndex) override {

359 assert(operandIndex >= 0 && operandIndex < getNumOperands());
360 return target.isVectorRegister();
361 }

362 bool isCondRegister(int operandIndex) {

362 bool isCondRegister(int operandIndex) override {

363 assert(operandIndex >= 0 && operandIndex < getNumOperands());
364 return target.isCondRegister();
365 }

366 bool isScalarRegister(int operandIndex) {

366 bool isScalarRegister(int operandIndex) override {

367 assert(operandIndex >= 0 && operandIndex < getNumOperands());
368 return target.isScalarRegister();
369 }

370 bool isSrcOperand(int operandIndex) {

370 bool isSrcOperand(int operandIndex) override {

371 assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
372 return true;
373 }

374 bool isDstOperand(int operandIndex) { return false; }
375 int getOperandSize(int operandIndex) {

374 bool isDstOperand(int operandIndex) override { return false; }
375 int getOperandSize(int operandIndex) override {

376 assert(operandIndex >= 0 && operandIndex < getNumOperands());
377 return target.opSize();
378 }

379 int getRegisterIndex(int operandIndex) {

379 int getRegisterIndex(int operandIndex) override {

380 assert(operandIndex >= 0 && operandIndex < getNumOperands());
381 return target.regIndex();
382 }

383 int getNumOperands() { return 1; }

383 int getNumOperands() override { return 1; }