gpu_isa.hh (13557:fc33e6048b25) gpu_isa.hh (13593:4164fea26cbb)
1/*
2 * Copyright (c) 2016 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 31 unchanged lines hidden (view full) ---

40
41#include "arch/hsail/gpu_types.hh"
42#include "base/logging.hh"
43#include "base/types.hh"
44#include "gpu-compute/misc.hh"
45
46namespace HsailISA
47{
1/*
2 * Copyright (c) 2016 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

--- 31 unchanged lines hidden (view full) ---

40
41#include "arch/hsail/gpu_types.hh"
42#include "base/logging.hh"
43#include "base/types.hh"
44#include "gpu-compute/misc.hh"
45
46namespace HsailISA
47{
48 typedef uint64_t MiscReg;
49
50 class GPUISA
51 {
52 public:
53 GPUISA()
54 {
55 }
56
57 void
48 class GPUISA
49 {
50 public:
51 GPUISA()
52 {
53 }
54
55 void
58 writeMiscReg(int opIdx, MiscReg operandVal)
56 writeMiscReg(int opIdx, RegVal operandVal)
59 {
60 fatal("HSAIL does not implement misc registers yet\n");
61 }
62
57 {
58 fatal("HSAIL does not implement misc registers yet\n");
59 }
60
63 MiscReg
61 RegVal
64 readMiscReg(int opIdx) const
65 {
66 fatal("HSAIL does not implement misc registers yet\n");
67 }
68
69 bool hasScalarUnit() const { return false; }
70
71 uint32_t
72 advancePC(uint32_t old_pc, GPUDynInstPtr gpuDynInst)
73 {
74 return old_pc + sizeof(RawMachInst);
75 }
76 };
77}
78
79#endif // __ARCH_HSAIL_GPU_ISA_HH__
62 readMiscReg(int opIdx) const
63 {
64 fatal("HSAIL does not implement misc registers yet\n");
65 }
66
67 bool hasScalarUnit() const { return false; }
68
69 uint32_t
70 advancePC(uint32_t old_pc, GPUDynInstPtr gpuDynInst)
71 {
72 return old_pc + sizeof(RawMachInst);
73 }
74 };
75}
76
77#endif // __ARCH_HSAIL_GPU_ISA_HH__