gpu_isa.hh (11697:c63431b7bbeb) gpu_isa.hh (11883:3bfed693ff22)
1/*
2 * Copyright (c) 2016 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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37#define __ARCH_HSAIL_GPU_ISA_HH__
38
39#include <cstdint>
40
41#include "arch/hsail/gpu_types.hh"
42#include "base/misc.hh"
43#include "gpu-compute/misc.hh"
44
1/*
2 * Copyright (c) 2016 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:

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37#define __ARCH_HSAIL_GPU_ISA_HH__
38
39#include <cstdint>
40
41#include "arch/hsail/gpu_types.hh"
42#include "base/misc.hh"
43#include "gpu-compute/misc.hh"
44
45class Wavefront;
46
47namespace HsailISA
48{
49 typedef uint64_t MiscReg;
50
51 class GPUISA
52 {
53 public:
45namespace HsailISA
46{
47 typedef uint64_t MiscReg;
48
49 class GPUISA
50 {
51 public:
54 GPUISA(Wavefront &wf) : wavefront(wf)
52 GPUISA()
55 {
56 }
57
58 void
59 writeMiscReg(int opIdx, MiscReg operandVal)
60 {
61 fatal("HSAIL does not implement misc registers yet\n");
62 }

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69
70 bool hasScalarUnit() const { return false; }
71
72 uint32_t
73 advancePC(uint32_t old_pc, GPUDynInstPtr gpuDynInst)
74 {
75 return old_pc + sizeof(RawMachInst);
76 }
53 {
54 }
55
56 void
57 writeMiscReg(int opIdx, MiscReg operandVal)
58 {
59 fatal("HSAIL does not implement misc registers yet\n");
60 }

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67
68 bool hasScalarUnit() const { return false; }
69
70 uint32_t
71 advancePC(uint32_t old_pc, GPUDynInstPtr gpuDynInst)
72 {
73 return old_pc + sizeof(RawMachInst);
74 }
77
78 private:
79 Wavefront &wavefront;
80 };
81}
82
83#endif // __ARCH_HSAIL_GPU_ISA_HH__
75 };
76}
77
78#endif // __ARCH_HSAIL_GPU_ISA_HH__