gen.py (11639:2e8d4bd8108d) gen.py (11643:42a1873be45c)
1#! /usr/bin/python
2
3#
4# Copyright (c) 2015 Advanced Micro Devices, Inc.
5# All rights reserved.
6#
7# For use for simulation and test purposes only
8#

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750 'w->workItemId[src0][lane] + (w->workGroupId[src0] * w->workGroupSz[src0])')
751gen_special('WorkGroupId', 'w->workGroupId[src0]')
752gen_special('WorkGroupSize', 'w->workGroupSz[src0]')
753gen_special('CurrentWorkGroupSize', 'w->workGroupSz[src0]')
754gen_special('GridSize', 'w->gridSz[src0]')
755gen_special('GridGroups',
756 'divCeil(w->gridSz[src0],w->workGroupSz[src0])')
757gen_special('LaneId', 'lane')
1#! /usr/bin/python
2
3#
4# Copyright (c) 2015 Advanced Micro Devices, Inc.
5# All rights reserved.
6#
7# For use for simulation and test purposes only
8#

--- 741 unchanged lines hidden (view full) ---

750 'w->workItemId[src0][lane] + (w->workGroupId[src0] * w->workGroupSz[src0])')
751gen_special('WorkGroupId', 'w->workGroupId[src0]')
752gen_special('WorkGroupSize', 'w->workGroupSz[src0]')
753gen_special('CurrentWorkGroupSize', 'w->workGroupSz[src0]')
754gen_special('GridSize', 'w->gridSz[src0]')
755gen_special('GridGroups',
756 'divCeil(w->gridSz[src0],w->workGroupSz[src0])')
757gen_special('LaneId', 'lane')
758gen_special('WaveId', 'w->dynWaveId')
758gen_special('WaveId', 'w->wfId')
759gen_special('Clock', 'w->computeUnit->shader->tick_cnt', 'U64')
760
761# gen_special('CU'', ')
762
763gen('Ret', base_class='SpecialInstNoSrcNoDest')
764gen('Barrier', base_class='SpecialInstNoSrcNoDest')
765gen('MemFence', base_class='SpecialInstNoSrcNoDest')
766

--- 40 unchanged lines hidden --- 		759gen_special('Clock', 'w->computeUnit->shader->tick_cnt', 'U64')
760
761# gen_special('CU'', ')
762
763gen('Ret', base_class='SpecialInstNoSrcNoDest')
764gen('Barrier', base_class='SpecialInstNoSrcNoDest')
765gen('MemFence', base_class='SpecialInstNoSrcNoDest')
766

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