vec_reg.hh (13119:398a93017471) vec_reg.hh (13610:5d5404ac6288)
1/*
2 * Copyright (c) 2015-2016, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 634 unchanged lines hidden (view full) ---

643 if (2 * i < value.size())
644 b = stoul(value.substr(i * 2, 2), nullptr, 16);
645 v.template raw_ptr<uint8_t>()[i] = b;
646 }
647 return true;
648}
649/** @} */
650
1/*
2 * Copyright (c) 2015-2016, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 634 unchanged lines hidden (view full) ---

643 if (2 * i < value.size())
644 b = stoul(value.substr(i * 2, 2), nullptr, 16);
645 v.template raw_ptr<uint8_t>()[i] = b;
646 }
647 return true;
648}
649/** @} */
650
651/**
652 * Dummy type aliases and constants for architectures that do not implement
653 * vector registers.
654 */
655/** @{ */
656using DummyVecElem = uint32_t;
657constexpr unsigned DummyNumVecElemPerVecReg = 2;
658using DummyVecReg = VecRegT<DummyVecElem, DummyNumVecElemPerVecReg, false>;
659using DummyConstVecReg = VecRegT<DummyVecElem, DummyNumVecElemPerVecReg, true>;
660using DummyVecRegContainer = DummyVecReg::Container;
661constexpr size_t DummyVecRegSizeBytes = DummyNumVecElemPerVecReg *
662 sizeof(DummyVecElem);
663/** @} */
664
651#endif /* __ARCH_GENERIC_VEC_REG_HH__ */
665#endif /* __ARCH_GENERIC_VEC_REG_HH__ */