1/*
2 * Copyright (c) 2010 Gabe Black
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_GENERIC_TYPES_HH__
32#define __ARCH_GENERIC_TYPES_HH__
33
34#include <iostream>
35
36#include "base/trace.hh"
37#include "base/types.hh"
38#include "sim/serialize.hh"
39
| 1/*
2 * Copyright (c) 2010 Gabe Black
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_GENERIC_TYPES_HH__
32#define __ARCH_GENERIC_TYPES_HH__
33
34#include <iostream>
35
36#include "base/trace.hh"
37#include "base/types.hh"
38#include "sim/serialize.hh"
39
|
40namespace GenericISA
41{
42
43// The guaranteed interface.
44class PCStateBase : public Serializable
45{
46 protected:
47 Addr _pc;
48 Addr _npc;
49
50 PCStateBase() : _pc(0), _npc(0) {}
51 PCStateBase(Addr val) : _pc(0), _npc(0) { set(val); }
52
53 public:
54 /**
55 * Returns the memory address the bytes of this instruction came from.
56 *
57 * @return Memory address of the current instruction's encoding.
58 */
59 Addr
60 instAddr() const
61 {
62 return _pc;
63 }
64
65 /**
66 * Returns the memory address the bytes of the next instruction came from.
67 *
68 * @return Memory address of the next instruction's encoding.
69 */
70 Addr
71 nextInstAddr() const
72 {
73 return _npc;
74 }
75
76 /**
77 * Returns the current micropc.
78 *
79 * @return The current micropc.
80 */
81 MicroPC
82 microPC() const
83 {
84 return 0;
85 }
86
87 /**
88 * Force this PC to reflect a particular value, resetting all its other
89 * fields around it. This is useful for in place (re)initialization.
90 *
91 * @param val The value to set the PC to.
92 */
93 void set(Addr val);
94
95 bool
96 operator == (const PCStateBase &opc) const
97 {
98 return _pc == opc._pc && _npc == opc._npc;
99 }
100
101 bool
102 operator != (const PCStateBase &opc) const
103 {
104 return !(*this == opc);
105 }
106
107 void
108 serialize(CheckpointOut &cp) const override
109 {
110 SERIALIZE_SCALAR(_pc);
111 SERIALIZE_SCALAR(_npc);
112 }
113
114 void
115 unserialize(CheckpointIn &cp) override
116 {
117 UNSERIALIZE_SCALAR(_pc);
118 UNSERIALIZE_SCALAR(_npc);
119 }
120};
121
122
123/*
124 * Different flavors of PC state. Only ISA specific code should rely on
125 * any particular type of PC state being available. All other code should
126 * use the interface above.
127 */
128
129// The most basic type of PC.
130template <class MachInst>
131class SimplePCState : public PCStateBase
132{
133 protected:
134 typedef PCStateBase Base;
135
136 public:
137
138 Addr pc() const { return _pc; }
139 void pc(Addr val) { _pc = val; }
140
141 Addr npc() const { return _npc; }
142 void npc(Addr val) { _npc = val; }
143
144 void
145 set(Addr val)
146 {
147 pc(val);
148 npc(val + sizeof(MachInst));
149 };
150
151 void
152 setNPC(Addr val)
153 {
154 npc(val);
155 }
156
157 SimplePCState() {}
158 SimplePCState(Addr val) { set(val); }
159
160 bool
161 branching() const
162 {
163 return this->npc() != this->pc() + sizeof(MachInst);
164 }
165
166 // Advance the PC.
167 void
168 advance()
169 {
170 _pc = _npc;
171 _npc += sizeof(MachInst);
172 }
173};
174
175template <class MachInst>
176std::ostream &
177operator<<(std::ostream & os, const SimplePCState<MachInst> &pc)
178{
179 ccprintf(os, "(%#x=>%#x)", pc.pc(), pc.npc());
180 return os;
181}
182
183// A PC and microcode PC.
184template <class MachInst>
185class UPCState : public SimplePCState<MachInst>
186{
187 protected:
188 typedef SimplePCState<MachInst> Base;
189
190 MicroPC _upc;
191 MicroPC _nupc;
192
193 public:
194
195 MicroPC upc() const { return _upc; }
196 void upc(MicroPC val) { _upc = val; }
197
198 MicroPC nupc() const { return _nupc; }
199 void nupc(MicroPC val) { _nupc = val; }
200
201 MicroPC
202 microPC() const
203 {
204 return _upc;
205 }
206
207 void
208 set(Addr val)
209 {
210 Base::set(val);
211 upc(0);
212 nupc(1);
213 }
214
215 UPCState() : _upc(0), _nupc(0) {}
216 UPCState(Addr val) : _upc(0), _nupc(0) { set(val); }
217
218 bool
219 branching() const
220 {
221 return this->npc() != this->pc() + sizeof(MachInst) ||
222 this->nupc() != this->upc() + 1;
223 }
224
225 // Advance the upc within the instruction.
226 void
227 uAdvance()
228 {
229 _upc = _nupc;
230 _nupc++;
231 }
232
233 // End the macroop by resetting the upc and advancing the regular pc.
234 void
235 uEnd()
236 {
237 this->advance();
238 _upc = 0;
239 _nupc = 1;
240 }
241
242 bool
243 operator == (const UPCState<MachInst> &opc) const
244 {
245 return Base::_pc == opc._pc &&
246 Base::_npc == opc._npc &&
247 _upc == opc._upc && _nupc == opc._nupc;
248 }
249
250 bool
251 operator != (const UPCState<MachInst> &opc) const
252 {
253 return !(*this == opc);
254 }
255
256 void
257 serialize(CheckpointOut &cp) const override
258 {
259 Base::serialize(cp);
260 SERIALIZE_SCALAR(_upc);
261 SERIALIZE_SCALAR(_nupc);
262 }
263
264 void
265 unserialize(CheckpointIn &cp) override
266 {
267 Base::unserialize(cp);
268 UNSERIALIZE_SCALAR(_upc);
269 UNSERIALIZE_SCALAR(_nupc);
270 }
271};
272
273template <class MachInst>
274std::ostream &
275operator<<(std::ostream & os, const UPCState<MachInst> &pc)
276{
277 ccprintf(os, "(%#x=>%#x).(%d=>%d)",
278 pc.pc(), pc.npc(), pc.upc(), pc.nupc());
279 return os;
280}
281
282// A PC with a delay slot.
283template <class MachInst>
284class DelaySlotPCState : public SimplePCState<MachInst>
285{
286 protected:
287 typedef SimplePCState<MachInst> Base;
288
289 Addr _nnpc;
290
291 public:
292
293 Addr nnpc() const { return _nnpc; }
294 void nnpc(Addr val) { _nnpc = val; }
295
296 void
297 set(Addr val)
298 {
299 Base::set(val);
300 nnpc(val + 2 * sizeof(MachInst));
301 }
302
303 DelaySlotPCState() {}
304 DelaySlotPCState(Addr val) { set(val); }
305
306 bool
307 branching() const
308 {
309 return !(this->nnpc() == this->npc() + sizeof(MachInst) &&
310 (this->npc() == this->pc() + sizeof(MachInst) ||
311 this->npc() == this->pc() + 2 * sizeof(MachInst)));
312 }
313
314 // Advance the PC.
315 void
316 advance()
317 {
318 Base::_pc = Base::_npc;
319 Base::_npc = _nnpc;
320 _nnpc += sizeof(MachInst);
321 }
322
323 bool
324 operator == (const DelaySlotPCState<MachInst> &opc) const
325 {
326 return Base::_pc == opc._pc &&
327 Base::_npc == opc._npc &&
328 _nnpc == opc._nnpc;
329 }
330
331 bool
332 operator != (const DelaySlotPCState<MachInst> &opc) const
333 {
334 return !(*this == opc);
335 }
336
337 void
338 serialize(CheckpointOut &cp) const override
339 {
340 Base::serialize(cp);
341 SERIALIZE_SCALAR(_nnpc);
342 }
343
344 void
345 unserialize(CheckpointIn &cp) override
346 {
347 Base::unserialize(cp);
348 UNSERIALIZE_SCALAR(_nnpc);
349 }
350};
351
352template <class MachInst>
353std::ostream &
354operator<<(std::ostream & os, const DelaySlotPCState<MachInst> &pc)
355{
356 ccprintf(os, "(%#x=>%#x=>%#x)",
357 pc.pc(), pc.npc(), pc.nnpc());
358 return os;
359}
360
361// A PC with a delay slot and a microcode PC.
362template <class MachInst>
363class DelaySlotUPCState : public DelaySlotPCState<MachInst>
364{
365 protected:
366 typedef DelaySlotPCState<MachInst> Base;
367
368 MicroPC _upc;
369 MicroPC _nupc;
370
371 public:
372
373 MicroPC upc() const { return _upc; }
374 void upc(MicroPC val) { _upc = val; }
375
376 MicroPC nupc() const { return _nupc; }
377 void nupc(MicroPC val) { _nupc = val; }
378
379 MicroPC
380 microPC() const
381 {
382 return _upc;
383 }
384
385 void
386 set(Addr val)
387 {
388 Base::set(val);
389 upc(0);
390 nupc(1);
391 }
392
393 DelaySlotUPCState() {}
394 DelaySlotUPCState(Addr val) { set(val); }
395
396 bool
397 branching() const
398 {
399 return Base::branching() || this->nupc() != this->upc() + 1;
400 }
401
402 // Advance the upc within the instruction.
403 void
404 uAdvance()
405 {
406 _upc = _nupc;
407 _nupc++;
408 }
409
410 // End the macroop by resetting the upc and advancing the regular pc.
411 void
412 uEnd()
413 {
414 this->advance();
415 _upc = 0;
416 _nupc = 1;
417 }
418
419 bool
420 operator == (const DelaySlotUPCState<MachInst> &opc) const
421 {
422 return Base::_pc == opc._pc &&
423 Base::_npc == opc._npc &&
424 Base::_nnpc == opc._nnpc &&
425 _upc == opc._upc && _nupc == opc._nupc;
426 }
427
428 bool
429 operator != (const DelaySlotUPCState<MachInst> &opc) const
430 {
431 return !(*this == opc);
432 }
433
434 void
435 serialize(CheckpointOut &cp) const override
436 {
437 Base::serialize(cp);
438 SERIALIZE_SCALAR(_upc);
439 SERIALIZE_SCALAR(_nupc);
440 }
441
442 void
443 unserialize(CheckpointIn &cp) override
444 {
445 Base::unserialize(cp);
446 UNSERIALIZE_SCALAR(_upc);
447 UNSERIALIZE_SCALAR(_nupc);
448 }
449};
450
451template <class MachInst>
452std::ostream &
453operator<<(std::ostream & os, const DelaySlotUPCState<MachInst> &pc)
454{
455 ccprintf(os, "(%#x=>%#x=>%#x).(%d=>%d)",
456 pc.pc(), pc.npc(), pc.nnpc(), pc.upc(), pc.nupc());
457 return os;
458}
459
460}
461
462#endif
| 43namespace GenericISA
44{
45
46// The guaranteed interface.
47class PCStateBase : public Serializable
48{
49 protected:
50 Addr _pc;
51 Addr _npc;
52
53 PCStateBase() : _pc(0), _npc(0) {}
54 PCStateBase(Addr val) : _pc(0), _npc(0) { set(val); }
55
56 public:
57 /**
58 * Returns the memory address the bytes of this instruction came from.
59 *
60 * @return Memory address of the current instruction's encoding.
61 */
62 Addr
63 instAddr() const
64 {
65 return _pc;
66 }
67
68 /**
69 * Returns the memory address the bytes of the next instruction came from.
70 *
71 * @return Memory address of the next instruction's encoding.
72 */
73 Addr
74 nextInstAddr() const
75 {
76 return _npc;
77 }
78
79 /**
80 * Returns the current micropc.
81 *
82 * @return The current micropc.
83 */
84 MicroPC
85 microPC() const
86 {
87 return 0;
88 }
89
90 /**
91 * Force this PC to reflect a particular value, resetting all its other
92 * fields around it. This is useful for in place (re)initialization.
93 *
94 * @param val The value to set the PC to.
95 */
96 void set(Addr val);
97
98 bool
99 operator == (const PCStateBase &opc) const
100 {
101 return _pc == opc._pc && _npc == opc._npc;
102 }
103
104 bool
105 operator != (const PCStateBase &opc) const
106 {
107 return !(*this == opc);
108 }
109
110 void
111 serialize(CheckpointOut &cp) const override
112 {
113 SERIALIZE_SCALAR(_pc);
114 SERIALIZE_SCALAR(_npc);
115 }
116
117 void
118 unserialize(CheckpointIn &cp) override
119 {
120 UNSERIALIZE_SCALAR(_pc);
121 UNSERIALIZE_SCALAR(_npc);
122 }
123};
124
125
126/*
127 * Different flavors of PC state. Only ISA specific code should rely on
128 * any particular type of PC state being available. All other code should
129 * use the interface above.
130 */
131
132// The most basic type of PC.
133template <class MachInst>
134class SimplePCState : public PCStateBase
135{
136 protected:
137 typedef PCStateBase Base;
138
139 public:
140
141 Addr pc() const { return _pc; }
142 void pc(Addr val) { _pc = val; }
143
144 Addr npc() const { return _npc; }
145 void npc(Addr val) { _npc = val; }
146
147 void
148 set(Addr val)
149 {
150 pc(val);
151 npc(val + sizeof(MachInst));
152 };
153
154 void
155 setNPC(Addr val)
156 {
157 npc(val);
158 }
159
160 SimplePCState() {}
161 SimplePCState(Addr val) { set(val); }
162
163 bool
164 branching() const
165 {
166 return this->npc() != this->pc() + sizeof(MachInst);
167 }
168
169 // Advance the PC.
170 void
171 advance()
172 {
173 _pc = _npc;
174 _npc += sizeof(MachInst);
175 }
176};
177
178template <class MachInst>
179std::ostream &
180operator<<(std::ostream & os, const SimplePCState<MachInst> &pc)
181{
182 ccprintf(os, "(%#x=>%#x)", pc.pc(), pc.npc());
183 return os;
184}
185
186// A PC and microcode PC.
187template <class MachInst>
188class UPCState : public SimplePCState<MachInst>
189{
190 protected:
191 typedef SimplePCState<MachInst> Base;
192
193 MicroPC _upc;
194 MicroPC _nupc;
195
196 public:
197
198 MicroPC upc() const { return _upc; }
199 void upc(MicroPC val) { _upc = val; }
200
201 MicroPC nupc() const { return _nupc; }
202 void nupc(MicroPC val) { _nupc = val; }
203
204 MicroPC
205 microPC() const
206 {
207 return _upc;
208 }
209
210 void
211 set(Addr val)
212 {
213 Base::set(val);
214 upc(0);
215 nupc(1);
216 }
217
218 UPCState() : _upc(0), _nupc(0) {}
219 UPCState(Addr val) : _upc(0), _nupc(0) { set(val); }
220
221 bool
222 branching() const
223 {
224 return this->npc() != this->pc() + sizeof(MachInst) ||
225 this->nupc() != this->upc() + 1;
226 }
227
228 // Advance the upc within the instruction.
229 void
230 uAdvance()
231 {
232 _upc = _nupc;
233 _nupc++;
234 }
235
236 // End the macroop by resetting the upc and advancing the regular pc.
237 void
238 uEnd()
239 {
240 this->advance();
241 _upc = 0;
242 _nupc = 1;
243 }
244
245 bool
246 operator == (const UPCState<MachInst> &opc) const
247 {
248 return Base::_pc == opc._pc &&
249 Base::_npc == opc._npc &&
250 _upc == opc._upc && _nupc == opc._nupc;
251 }
252
253 bool
254 operator != (const UPCState<MachInst> &opc) const
255 {
256 return !(*this == opc);
257 }
258
259 void
260 serialize(CheckpointOut &cp) const override
261 {
262 Base::serialize(cp);
263 SERIALIZE_SCALAR(_upc);
264 SERIALIZE_SCALAR(_nupc);
265 }
266
267 void
268 unserialize(CheckpointIn &cp) override
269 {
270 Base::unserialize(cp);
271 UNSERIALIZE_SCALAR(_upc);
272 UNSERIALIZE_SCALAR(_nupc);
273 }
274};
275
276template <class MachInst>
277std::ostream &
278operator<<(std::ostream & os, const UPCState<MachInst> &pc)
279{
280 ccprintf(os, "(%#x=>%#x).(%d=>%d)",
281 pc.pc(), pc.npc(), pc.upc(), pc.nupc());
282 return os;
283}
284
285// A PC with a delay slot.
286template <class MachInst>
287class DelaySlotPCState : public SimplePCState<MachInst>
288{
289 protected:
290 typedef SimplePCState<MachInst> Base;
291
292 Addr _nnpc;
293
294 public:
295
296 Addr nnpc() const { return _nnpc; }
297 void nnpc(Addr val) { _nnpc = val; }
298
299 void
300 set(Addr val)
301 {
302 Base::set(val);
303 nnpc(val + 2 * sizeof(MachInst));
304 }
305
306 DelaySlotPCState() {}
307 DelaySlotPCState(Addr val) { set(val); }
308
309 bool
310 branching() const
311 {
312 return !(this->nnpc() == this->npc() + sizeof(MachInst) &&
313 (this->npc() == this->pc() + sizeof(MachInst) ||
314 this->npc() == this->pc() + 2 * sizeof(MachInst)));
315 }
316
317 // Advance the PC.
318 void
319 advance()
320 {
321 Base::_pc = Base::_npc;
322 Base::_npc = _nnpc;
323 _nnpc += sizeof(MachInst);
324 }
325
326 bool
327 operator == (const DelaySlotPCState<MachInst> &opc) const
328 {
329 return Base::_pc == opc._pc &&
330 Base::_npc == opc._npc &&
331 _nnpc == opc._nnpc;
332 }
333
334 bool
335 operator != (const DelaySlotPCState<MachInst> &opc) const
336 {
337 return !(*this == opc);
338 }
339
340 void
341 serialize(CheckpointOut &cp) const override
342 {
343 Base::serialize(cp);
344 SERIALIZE_SCALAR(_nnpc);
345 }
346
347 void
348 unserialize(CheckpointIn &cp) override
349 {
350 Base::unserialize(cp);
351 UNSERIALIZE_SCALAR(_nnpc);
352 }
353};
354
355template <class MachInst>
356std::ostream &
357operator<<(std::ostream & os, const DelaySlotPCState<MachInst> &pc)
358{
359 ccprintf(os, "(%#x=>%#x=>%#x)",
360 pc.pc(), pc.npc(), pc.nnpc());
361 return os;
362}
363
364// A PC with a delay slot and a microcode PC.
365template <class MachInst>
366class DelaySlotUPCState : public DelaySlotPCState<MachInst>
367{
368 protected:
369 typedef DelaySlotPCState<MachInst> Base;
370
371 MicroPC _upc;
372 MicroPC _nupc;
373
374 public:
375
376 MicroPC upc() const { return _upc; }
377 void upc(MicroPC val) { _upc = val; }
378
379 MicroPC nupc() const { return _nupc; }
380 void nupc(MicroPC val) { _nupc = val; }
381
382 MicroPC
383 microPC() const
384 {
385 return _upc;
386 }
387
388 void
389 set(Addr val)
390 {
391 Base::set(val);
392 upc(0);
393 nupc(1);
394 }
395
396 DelaySlotUPCState() {}
397 DelaySlotUPCState(Addr val) { set(val); }
398
399 bool
400 branching() const
401 {
402 return Base::branching() || this->nupc() != this->upc() + 1;
403 }
404
405 // Advance the upc within the instruction.
406 void
407 uAdvance()
408 {
409 _upc = _nupc;
410 _nupc++;
411 }
412
413 // End the macroop by resetting the upc and advancing the regular pc.
414 void
415 uEnd()
416 {
417 this->advance();
418 _upc = 0;
419 _nupc = 1;
420 }
421
422 bool
423 operator == (const DelaySlotUPCState<MachInst> &opc) const
424 {
425 return Base::_pc == opc._pc &&
426 Base::_npc == opc._npc &&
427 Base::_nnpc == opc._nnpc &&
428 _upc == opc._upc && _nupc == opc._nupc;
429 }
430
431 bool
432 operator != (const DelaySlotUPCState<MachInst> &opc) const
433 {
434 return !(*this == opc);
435 }
436
437 void
438 serialize(CheckpointOut &cp) const override
439 {
440 Base::serialize(cp);
441 SERIALIZE_SCALAR(_upc);
442 SERIALIZE_SCALAR(_nupc);
443 }
444
445 void
446 unserialize(CheckpointIn &cp) override
447 {
448 Base::unserialize(cp);
449 UNSERIALIZE_SCALAR(_upc);
450 UNSERIALIZE_SCALAR(_nupc);
451 }
452};
453
454template <class MachInst>
455std::ostream &
456operator<<(std::ostream & os, const DelaySlotUPCState<MachInst> &pc)
457{
458 ccprintf(os, "(%#x=>%#x=>%#x).(%d=>%d)",
459 pc.pc(), pc.npc(), pc.nnpc(), pc.upc(), pc.nupc());
460 return os;
461}
462
463}
464
465#endif
|