1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42 43#ifndef __ARCH_GENERIC_TLB_HH__ 44#define __ARCH_GENERIC_TLB_HH__ 45 46#include "base/misc.hh" 47#include "mem/request.hh" 48#include "sim/sim_object.hh" 49 50class ThreadContext; 51class BaseMasterPort; 52 53class BaseTLB : public SimObject 54{ 55 protected: 56 BaseTLB(const Params *p) 57 : SimObject(p) 58 {} 59 60 public: 61 enum Mode { Read, Write, Execute }; 62 63 public: 64 virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 65 66 /** 67 * Remove all entries from the TLB 68 */ 69 virtual void flushAll() = 0; 70 71 /** 72 * Take over from an old tlb context 73 */ 74 virtual void takeOverFrom(BaseTLB *otlb) = 0; 75 76 /** 77 * Get the table walker master port if present. This is used for 78 * migrating port connections during a CPU takeOverFrom() 79 * call. For architectures that do not have a table walker, NULL 80 * is returned, hence the use of a pointer rather than a 81 * reference. 82 * 83 * @return A pointer to the walker master port or NULL if not present 84 */ 85 virtual BaseMasterPort* getMasterPort() { return NULL; } 86 87 void memInvalidate() { flushAll(); } 88 89 class Translation 90 { 91 public: 92 virtual ~Translation() 93 {} 94 95 /** 96 * Signal that the translation has been delayed due to a hw page table 97 * walk. 98 */ 99 virtual void markDelayed() = 0; 100 101 /* 102 * The memory for this object may be dynamically allocated, and it may 103 * be responsible for cleaning itself up which will happen in this 104 * function. Once it's called, the object is no longer valid. 105 */ 106 virtual void finish(const Fault &fault, RequestPtr req, 107 ThreadContext *tc, Mode mode) = 0; 108 109 /** This function is used by the page table walker to determine if it 110 * should translate the a pending request or if the underlying request 111 * has been squashed. 112 * @ return Is the instruction that requested this translation squashed? 113 */ 114 virtual bool squashed() const { return false; } 115 }; 116}; 117 118class GenericTLB : public BaseTLB 119{ 120 protected: 121 GenericTLB(const Params *p) 122 : BaseTLB(p) 123 {} 124 125 public:
| 1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 */ 42 43#ifndef __ARCH_GENERIC_TLB_HH__ 44#define __ARCH_GENERIC_TLB_HH__ 45 46#include "base/misc.hh" 47#include "mem/request.hh" 48#include "sim/sim_object.hh" 49 50class ThreadContext; 51class BaseMasterPort; 52 53class BaseTLB : public SimObject 54{ 55 protected: 56 BaseTLB(const Params *p) 57 : SimObject(p) 58 {} 59 60 public: 61 enum Mode { Read, Write, Execute }; 62 63 public: 64 virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 65 66 /** 67 * Remove all entries from the TLB 68 */ 69 virtual void flushAll() = 0; 70 71 /** 72 * Take over from an old tlb context 73 */ 74 virtual void takeOverFrom(BaseTLB *otlb) = 0; 75 76 /** 77 * Get the table walker master port if present. This is used for 78 * migrating port connections during a CPU takeOverFrom() 79 * call. For architectures that do not have a table walker, NULL 80 * is returned, hence the use of a pointer rather than a 81 * reference. 82 * 83 * @return A pointer to the walker master port or NULL if not present 84 */ 85 virtual BaseMasterPort* getMasterPort() { return NULL; } 86 87 void memInvalidate() { flushAll(); } 88 89 class Translation 90 { 91 public: 92 virtual ~Translation() 93 {} 94 95 /** 96 * Signal that the translation has been delayed due to a hw page table 97 * walk. 98 */ 99 virtual void markDelayed() = 0; 100 101 /* 102 * The memory for this object may be dynamically allocated, and it may 103 * be responsible for cleaning itself up which will happen in this 104 * function. Once it's called, the object is no longer valid. 105 */ 106 virtual void finish(const Fault &fault, RequestPtr req, 107 ThreadContext *tc, Mode mode) = 0; 108 109 /** This function is used by the page table walker to determine if it 110 * should translate the a pending request or if the underlying request 111 * has been squashed. 112 * @ return Is the instruction that requested this translation squashed? 113 */ 114 virtual bool squashed() const { return false; } 115 }; 116}; 117 118class GenericTLB : public BaseTLB 119{ 120 protected: 121 GenericTLB(const Params *p) 122 : BaseTLB(p) 123 {} 124 125 public:
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127 128 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 129 void translateTiming(RequestPtr req, ThreadContext *tc, 130 Translation *translation, Mode mode); 131 132 133 /** 134 * Do post-translation physical address finalization. 135 * 136 * This method is used by some architectures that need 137 * post-translation massaging of physical addresses. For example, 138 * X86 uses this to remap physical addresses in the APIC range to 139 * a range of physical memory not normally available to real x86 140 * implementations. 141 * 142 * @param req Request to updated in-place. 143 * @param tc Thread context that created the request. 144 * @param mode Request type (read/write/execute). 145 * @return A fault on failure, NoFault otherwise. 146 */ 147 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 148}; 149 150#endif // __ARCH_GENERIC_TLB_HH__
| 127 128 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 129 void translateTiming(RequestPtr req, ThreadContext *tc, 130 Translation *translation, Mode mode); 131 132 133 /** 134 * Do post-translation physical address finalization. 135 * 136 * This method is used by some architectures that need 137 * post-translation massaging of physical addresses. For example, 138 * X86 uses this to remap physical addresses in the APIC range to 139 * a range of physical memory not normally available to real x86 140 * implementations. 141 * 142 * @param req Request to updated in-place. 143 * @param tc Thread context that created the request. 144 * @param mode Request type (read/write/execute). 145 * @return A fault on failure, NoFault otherwise. 146 */ 147 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; 148}; 149 150#endif // __ARCH_GENERIC_TLB_HH__
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