mmapped_ipr.hh (9897:e105fbf799e7) mmapped_ipr.hh (9911:676d3dcf1cc2)
1/*
2 * Copyright (c) 2013 Andreas Sandberg
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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44
45namespace GenericISA
46{
47 /** @{ */
48 /**
49 * Memory requests with the MMAPPED_IPR flag are generally mapped
50 * to registers. There is a class of these registers that are
51 * internal to gem5, for example gem5 pseudo-ops in virtualized
1/*
2 * Copyright (c) 2013 Andreas Sandberg
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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44
45namespace GenericISA
46{
47 /** @{ */
48 /**
49 * Memory requests with the MMAPPED_IPR flag are generally mapped
50 * to registers. There is a class of these registers that are
51 * internal to gem5, for example gem5 pseudo-ops in virtualized
52 * mode.
53 *
54 * In order to make the IPR space manageable we always set bit 63
55 * (IPR_GENERIC) for accesses that should be handled by the
56 * generic ISA code. Architectures may use the rest of the IPR
57 * space internally.
52 * mode. Such IPRs always have the flag GENERIC_IPR set and are
53 * handled by this code.
58 */
59
54 */
55
60 /** Is this a generic IPR access? */
61 const Addr IPR_GENERIC = ULL(0x8000000000000000);
62
63 /** @{ */
64 /** Mask when extracting the class of a generic IPR */
65 const Addr IPR_CLASS_MASK = ULL(0x7FFF000000000000);
66 /** Shift amount when extracting the class of a generic IPR */
67 const int IPR_CLASS_SHIFT = 48;
56 /** Shift amount when extracting the class of a generic IPR */
57 const int IPR_CLASS_SHIFT = 48;
68 /** @} */
69
70 /** Mask to extract the offset in within a generic IPR class */
71 const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF);
72
73 /** gem5 pseudo-inst emulation.
74 *
75 * Read and writes to this class execute gem5
76 * pseudo-instructions. A write discards the return value of the

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89 *
90 * @param func Function ID to call.
91 * @param subfunc Sub-function, usually 0.
92 * @return Address in the IPR space corresponding to the call.
93 */
94 inline Addr
95 iprAddressPseudoInst(uint8_t func, uint8_t subfunc)
96 {
58
59 /** Mask to extract the offset in within a generic IPR class */
60 const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF);
61
62 /** gem5 pseudo-inst emulation.
63 *
64 * Read and writes to this class execute gem5
65 * pseudo-instructions. A write discards the return value of the

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78 *
79 * @param func Function ID to call.
80 * @param subfunc Sub-function, usually 0.
81 * @return Address in the IPR space corresponding to the call.
82 */
83 inline Addr
84 iprAddressPseudoInst(uint8_t func, uint8_t subfunc)
85 {
97 return IPR_GENERIC | (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT) |
86 return (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT) |
98 (func << 8) | subfunc;
99 }
100
101 /**
102 * Check if this is an platform independent IPR access
103 *
104 * Accesses to internal platform independent gem5 registers are
105 * handled by handleGenericIprRead() and
106 * handleGenericIprWrite(). This method determines if a packet
107 * should be routed to those functions instead of the platform
108 * specific code.
109 *
110 * @see handleGenericIprRead
111 * @see handleGenericIprWrite
112 */
113 inline bool
114 isGenericIprAccess(const Packet *pkt)
115 {
87 (func << 8) | subfunc;
88 }
89
90 /**
91 * Check if this is an platform independent IPR access
92 *
93 * Accesses to internal platform independent gem5 registers are
94 * handled by handleGenericIprRead() and
95 * handleGenericIprWrite(). This method determines if a packet
96 * should be routed to those functions instead of the platform
97 * specific code.
98 *
99 * @see handleGenericIprRead
100 * @see handleGenericIprWrite
101 */
102 inline bool
103 isGenericIprAccess(const Packet *pkt)
104 {
116 return pkt->getAddr() & IPR_GENERIC;
105 Request::Flags flags(pkt->req->getFlags());
106 return (flags & Request::MMAPPED_IPR) &&
107 (flags & Request::GENERIC_IPR);
117 }
118
119 /**
120 * Handle generic IPR reads
121 *
122 * @param xc Thread context of the current thread.
123 * @param pkt Packet from the CPU
124 * @return Latency in CPU cycles

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109
110 /**
111 * Handle generic IPR reads
112 *
113 * @param xc Thread context of the current thread.
114 * @param pkt Packet from the CPU
115 * @return Latency in CPU cycles

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