BaseTLB.py (13692:0cb587b75895) | BaseTLB.py (13714:35636064b7a1) |
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1# Copyright (c) 2008 The Hewlett-Packard Development Company 2# Copyright (c) 2018 Metempsy Technology Consulting 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Gabe Black 29# Ivan Pizarro 30 31from m5.params import * | 1# Copyright (c) 2008 The Hewlett-Packard Development Company 2# Copyright (c) 2018 Metempsy Technology Consulting 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Gabe Black 29# Ivan Pizarro 30 31from m5.params import * |
32from MemObject import MemObject | 32from m5.objects.MemObject import MemObject |
33 34class BaseTLB(MemObject): 35 type = 'BaseTLB' 36 abstract = True 37 cxx_header = "arch/generic/tlb.hh" 38 # Ports to connect with other TLB levels 39 slave = VectorSlavePort("Port closer to the CPU side") 40 master = MasterPort("Port closer to memory side") | 33 34class BaseTLB(MemObject): 35 type = 'BaseTLB' 36 abstract = True 37 cxx_header = "arch/generic/tlb.hh" 38 # Ports to connect with other TLB levels 39 slave = VectorSlavePort("Port closer to the CPU side") 40 master = MasterPort("Port closer to memory side") |