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> # Copyright (c) 2018 Metempsy Technology Consulting
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> # Ivan Pizarro
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< from m5.SimObject import SimObject
---
> from m5.params import *
> from MemObject import MemObject
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< class BaseTLB(SimObject):
---
> class BaseTLB(MemObject):
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> # Ports to connect with other TLB levels
> slave = VectorSlavePort("Port closer to the CPU side")
> master = MasterPort("Port closer to memory side")