vtophys.cc (8852:c744483edfcf) vtophys.cc (10037:5cac77888310)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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40 *
41 * Authors: Ali Saidi
42 * Nathan Binkert
43 * Stephen Hines
44 */
45
46#include <string>
47
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 29 unchanged lines hidden (view full) ---

40 *
41 * Authors: Ali Saidi
42 * Nathan Binkert
43 * Stephen Hines
44 */
45
46#include <string>
47
48#include "arch/arm/faults.hh"
48#include "arch/arm/table_walker.hh"
49#include "arch/arm/tlb.hh"
50#include "arch/arm/vtophys.hh"
51#include "base/chunk_generator.hh"
52#include "base/trace.hh"
53#include "cpu/thread_context.hh"
54#include "mem/fs_translating_port_proxy.hh"
55

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60ArmISA::vtophys(Addr vaddr)
61{
62 fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
63}
64
65Addr
66ArmISA::vtophys(ThreadContext *tc, Addr addr)
67{
49#include "arch/arm/table_walker.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/vtophys.hh"
52#include "base/chunk_generator.hh"
53#include "base/trace.hh"
54#include "cpu/thread_context.hh"
55#include "mem/fs_translating_port_proxy.hh"
56

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61ArmISA::vtophys(Addr vaddr)
62{
63 fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
64}
65
66Addr
67ArmISA::vtophys(ThreadContext *tc, Addr addr)
68{
68 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
69 if (!sctlr.m) {
70 // Translation is currently disabled PA == VA
71 return addr;
72 }
73 bool success;
74 Addr pa;
69 Fault fault;
70 // Set up a functional memory Request to pass to the TLB
71 // to get it to translate the vaddr to a paddr
72 Request req(0, addr, 64, 0x40, -1, 0, 0, 0);
75 ArmISA::TLB *tlb;
76
73 ArmISA::TLB *tlb;
74
77 // Check the TLBs far a translation
78 // It's possible that there is a validy translation in the tlb
75 // Check the TLBs for a translation
76 // It's possible that there is a valid translation in the tlb
79 // that is no loger valid in the page table in memory
80 // so we need to check here first
77 // that is no loger valid in the page table in memory
78 // so we need to check here first
79 //
80 // Calling translateFunctional invokes a table-walk if required
81 // so we should always succeed
81 tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
82 tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
82 success = tlb->translateFunctional(tc, addr, pa);
83 if (success)
84 return pa;
83 fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
84 if (fault == NoFault)
85 return req.getPaddr();
85
86 tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
86
87 tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
87 success = tlb->translateFunctional(tc, addr, pa);
88 if (success)
89 return pa;
88 fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
89 if (fault == NoFault)
90 return req.getPaddr();
90
91
91 // We've failed everything, so we need to do a
92 // hardware tlb walk without messing with any
93 // state
94
95 uint32_t N = tc->readMiscReg(MISCREG_TTBCR);
96 Addr ttbr;
97 if (N == 0 || !mbits(addr, 31, 32-N)) {
98 ttbr = tc->readMiscReg(MISCREG_TTBR0);
99 } else {
100 ttbr = tc->readMiscReg(MISCREG_TTBR1);
101 N = 0;
102 }
103
104 PortProxy &port = tc->getPhysProxy();
105 Addr l1desc_addr = mbits(ttbr, 31, 14-N) | (bits(addr,31-N,20) << 2);
106
107 TableWalker::L1Descriptor l1desc;
108 l1desc.data = port.read<uint32_t>(l1desc_addr);
109 if (l1desc.type() == TableWalker::L1Descriptor::Ignore ||
110 l1desc.type() == TableWalker::L1Descriptor::Reserved) {
111 warn("Unable to translate virtual address: %#x\n", addr);
112 return -1;
113 }
114 if (l1desc.type() == TableWalker::L1Descriptor::Section)
115 return l1desc.paddr(addr);
116
117 // Didn't find it at the first level, try againt
118 Addr l2desc_addr = l1desc.l2Addr() | (bits(addr, 19, 12) << 2);
119 TableWalker::L2Descriptor l2desc;
120 l2desc.data = port.read<uint32_t>(l2desc_addr);
121
122 if (l2desc.invalid()) {
123 warn("Unable to translate virtual address: %#x\n", addr);
124 return -1;
125 }
126
127 return l2desc.paddr(addr);
92 panic("Table walkers support functional accesses. We should never get here\n");
128}
129
130bool
131ArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
132{
133 if (vtophys(tc, vaddr) != -1)
134 return true;
135 return false;
136}
137
138
93}
94
95bool
96ArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
97{
98 if (vtophys(tc, vaddr) != -1)
99 return true;
100 return false;
101}
102
103