1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Nathan Binkert
43 * Stephen Hines
44 */
45
46#include <string>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/table_walker.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/vtophys.hh"
52#include "base/chunk_generator.hh"
53#include "base/trace.hh"
54#include "cpu/thread_context.hh"
55#include "mem/fs_translating_port_proxy.hh"
56
57using namespace std;
58using namespace ArmISA;
59
60Addr
61ArmISA::vtophys(Addr vaddr)
62{
63 fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
64}
65
| 1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Nathan Binkert
43 * Stephen Hines
44 */
45
46#include <string>
47
48#include "arch/arm/faults.hh"
49#include "arch/arm/table_walker.hh"
50#include "arch/arm/tlb.hh"
51#include "arch/arm/vtophys.hh"
52#include "base/chunk_generator.hh"
53#include "base/trace.hh"
54#include "cpu/thread_context.hh"
55#include "mem/fs_translating_port_proxy.hh"
56
57using namespace std;
58using namespace ArmISA;
59
60Addr
61ArmISA::vtophys(Addr vaddr)
62{
63 fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
64}
65
|
66Addr
67ArmISA::vtophys(ThreadContext *tc, Addr addr)
| 66static std::pair<bool, Addr>
67try_translate(ThreadContext *tc, Addr addr)
|
68{
69 Fault fault;
70 // Set up a functional memory Request to pass to the TLB
71 // to get it to translate the vaddr to a paddr
72 Request req(0, addr, 64, 0x40, -1, 0, 0, 0);
73 ArmISA::TLB *tlb;
74
75 // Check the TLBs for a translation
76 // It's possible that there is a valid translation in the tlb
77 // that is no loger valid in the page table in memory
78 // so we need to check here first
79 //
80 // Calling translateFunctional invokes a table-walk if required
81 // so we should always succeed
82 tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
83 fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
84 if (fault == NoFault)
| 68{
69 Fault fault;
70 // Set up a functional memory Request to pass to the TLB
71 // to get it to translate the vaddr to a paddr
72 Request req(0, addr, 64, 0x40, -1, 0, 0, 0);
73 ArmISA::TLB *tlb;
74
75 // Check the TLBs for a translation
76 // It's possible that there is a valid translation in the tlb
77 // that is no loger valid in the page table in memory
78 // so we need to check here first
79 //
80 // Calling translateFunctional invokes a table-walk if required
81 // so we should always succeed
82 tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
83 fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
84 if (fault == NoFault)
|
85 return req.getPaddr();
| 85 return std::make_pair(true, req.getPaddr());
|
86
87 tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
88 fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
89 if (fault == NoFault)
| 86
87 tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
88 fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
89 if (fault == NoFault)
|
90 return req.getPaddr();
| 90 return std::make_pair(true, req.getPaddr());
|
91
| 91
|
92 panic("Table walkers support functional accesses. We should never get here\n");
| 92 return std::make_pair(false, 0);
|
93}
94
| 93}
94
|
| 95Addr
96ArmISA::vtophys(ThreadContext *tc, Addr addr)
97{
98 const std::pair<bool, Addr> translation(try_translate(tc, addr));
99
100 if (translation.first)
101 return translation.second;
102 else
103 panic("Table walkers support functional accesses. We should never get here\n");
104}
105
|
95bool
96ArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
97{
| 106bool
107ArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
108{
|
98 if (vtophys(tc, vaddr) != -1)
99 return true;
100 return false;
| 109 const std::pair<bool, Addr> translation(try_translate(tc, vaddr));
110
111 return translation.first;
|
101}
102
103
| 112}
113
114
|