utility.cc (8886:5e8d2d7162b0) | utility.cc (8887:20ea02da9c53) |
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1/* 2 * Copyright (c) 2009-2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 29 unchanged lines hidden (view full) --- 38 */ 39 40 41#include "arch/arm/faults.hh" 42#include "arch/arm/isa_traits.hh" 43#include "arch/arm/tlb.hh" 44#include "arch/arm/utility.hh" 45#include "arch/arm/vtophys.hh" | 1/* 2 * Copyright (c) 2009-2010 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 29 unchanged lines hidden (view full) --- 38 */ 39 40 41#include "arch/arm/faults.hh" 42#include "arch/arm/isa_traits.hh" 43#include "arch/arm/tlb.hh" 44#include "arch/arm/utility.hh" 45#include "arch/arm/vtophys.hh" |
46#include "config/use_checker.hh" | 46#include "cpu/checker/cpu.hh" |
47#include "cpu/base.hh" 48#include "cpu/thread_context.hh" 49#include "mem/fs_translating_port_proxy.hh" 50#include "params/BaseCPU.hh" 51#include "sim/full_system.hh" 52 53namespace ArmISA { 54 --- 58 unchanged lines hidden (view full) --- 113 } 114} 115 116void 117skipFunction(ThreadContext *tc) 118{ 119 TheISA::PCState newPC = tc->pcState(); 120 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); | 47#include "cpu/base.hh" 48#include "cpu/thread_context.hh" 49#include "mem/fs_translating_port_proxy.hh" 50#include "params/BaseCPU.hh" 51#include "sim/full_system.hh" 52 53namespace ArmISA { 54 --- 58 unchanged lines hidden (view full) --- 113 } 114} 115 116void 117skipFunction(ThreadContext *tc) 118{ 119 TheISA::PCState newPC = tc->pcState(); 120 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); |
121#if USE_CHECKER 122 tc->pcStateNoRecord(newPC); 123#else 124 tc->pcState(newPC); 125#endif | 121 122 CheckerCPU *checker = tc->getCheckerCpuPtr(); 123 if (checker) { 124 tc->pcStateNoRecord(newPC); 125 } else { 126 tc->pcState(newPC); 127 } |
126} 127 128void 129copyRegs(ThreadContext *src, ThreadContext *dest) 130{ 131 int i; 132 133 int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode; --- 43 unchanged lines hidden --- | 128} 129 130void 131copyRegs(ThreadContext *src, ThreadContext *dest) 132{ 133 int i; 134 135 int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode; --- 43 unchanged lines hidden --- |