utility.cc (8733:64a7bf8fa56c) utility.cc (8782:10c9297e14d5)
1/*
2 * Copyright (c) 2009-2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
1/*
2 * Copyright (c) 2009-2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
43#include "arch/arm/tlb.hh"
43#include "arch/arm/utility.hh"
44#include "arch/arm/utility.hh"
44#include "config/use_checker.hh"
45#include "arch/arm/vtophys.hh"
45#include "cpu/thread_context.hh"
46#include "cpu/thread_context.hh"
47#include "mem/vport.hh"
48#include "sim/full_system.hh"
46
49
47#if FULL_SYSTEM
48#include "arch/arm/vtophys.hh"
49#include "mem/fs_translating_port_proxy.hh"
50#endif
51
52#include "arch/arm/tlb.hh"
53
54namespace ArmISA {
55
56void
57initCPU(ThreadContext *tc, int cpuId)
58{
59 // Reset CP15?? What does that mean -- ali
60
61 // FPEXC.EN = 0
62
63 static Fault reset = new Reset;
64 reset->invoke(tc);
65}
66
67uint64_t
68getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
69{
50namespace ArmISA {
51
52void
53initCPU(ThreadContext *tc, int cpuId)
54{
55 // Reset CP15?? What does that mean -- ali
56
57 // FPEXC.EN = 0
58
59 static Fault reset = new Reset;
60 reset->invoke(tc);
61}
62
63uint64_t
64getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
65{
70#if FULL_SYSTEM
71 if (size == (uint16_t)(-1))
72 size = ArmISA::MachineBytes;
73 if (fp)
74 panic("getArgument(): Floating point arguments not implemented\n");
66 if (FullSystem) {
67 if (size == (uint16_t)(-1))
68 size = ArmISA::MachineBytes;
69 if (fp)
70 panic("getArgument(): Floating point arguments not implemented\n");
75
71
76 if (number < NumArgumentRegs) {
77 // If the argument is 64 bits, it must be in an even regiser number
78 // Increment the number here if it isn't even
79 if (size == sizeof(uint64_t)) {
80 if ((number % 2) != 0)
81 number++;
82 // Read the two halves of the data
83 // number is inc here to get the second half of the 64 bit reg
84 uint64_t tmp;
85 tmp = tc->readIntReg(number++);
86 tmp |= tc->readIntReg(number) << 32;
87 return tmp;
72 if (number < NumArgumentRegs) {
73 // If the argument is 64 bits, it must be in an even regiser
74 // number. Increment the number here if it isn't even.
75 if (size == sizeof(uint64_t)) {
76 if ((number % 2) != 0)
77 number++;
78 // Read the two halves of the data. Number is inc here to
79 // get the second half of the 64 bit reg.
80 uint64_t tmp;
81 tmp = tc->readIntReg(number++);
82 tmp |= tc->readIntReg(number) << 32;
83 return tmp;
84 } else {
85 return tc->readIntReg(number);
86 }
88 } else {
87 } else {
89 return tc->readIntReg(number);
90 }
91 } else {
92 Addr sp = tc->readIntReg(StackPointerReg);
93 FSTranslatingPortProxy* vp = tc->getVirtProxy();
94 uint64_t arg;
95 if (size == sizeof(uint64_t)) {
96 // If the argument is even it must be aligned
97 if ((number % 2) != 0)
88 Addr sp = tc->readIntReg(StackPointerReg);
89 VirtualPort *vp = tc->getVirtPort();
90 uint64_t arg;
91 if (size == sizeof(uint64_t)) {
92 // If the argument is even it must be aligned
93 if ((number % 2) != 0)
94 number++;
95 arg = vp->read<uint64_t>(sp +
96 (number-NumArgumentRegs) * sizeof(uint32_t));
97 // since two 32 bit args == 1 64 bit arg, increment number
98 number++;
98 number++;
99 arg = vp->read<uint64_t>(sp +
100 (number-NumArgumentRegs) * sizeof(uint32_t));
101 // since two 32 bit args == 1 64 bit arg, increment number
102 number++;
103 } else {
104 arg = vp->read<uint32_t>(sp +
105 (number-NumArgumentRegs) * sizeof(uint32_t));
99 } else {
100 arg = vp->read<uint32_t>(sp +
101 (number-NumArgumentRegs) * sizeof(uint32_t));
102 }
103 return arg;
106 }
104 }
107 return arg;
105 } else {
106 panic("getArgument() only implemented for full system mode.\n");
107 M5_DUMMY_RETURN
108 }
108 }
109#else
110 panic("getArgument() only implemented for FULL_SYSTEM\n");
111 M5_DUMMY_RETURN
112#endif
113}
114
115void
116skipFunction(ThreadContext *tc)
117{
118 TheISA::PCState newPC = tc->pcState();
119 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
109}
110
111void
112skipFunction(ThreadContext *tc)
113{
114 TheISA::PCState newPC = tc->pcState();
115 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
120#if USE_CHECKER
121 tc->pcStateNoRecord(newPC);
122#else
123 tc->pcState(newPC);
116 tc->pcState(newPC);
124#endif
125}
126
127void
128copyRegs(ThreadContext *src, ThreadContext *dest)
129{
130 int i;
131
132 int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode;

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118
119void
120copyRegs(ThreadContext *src, ThreadContext *dest)
121{
122 int i;
123
124 int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode;

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