| utility.cc (14020:c9bf7a011602) | utility.cc (14171:58d343fa3194) |
|---|---|
| 1/* 2 * Copyright (c) 2009-2014, 2016-2019 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 327 unchanged lines hidden (view full) --- 336 || (have_el2 337 && !isSecureBelowEL3(tc) && hcr.rw == 0)); 338 339 // Only know if EL0 using AArch32 from PSTATE 340 if (el == EL0 && !aarch32_at_el1) { 341 // EL0 controlled by PSTATE 342 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 343 | 1/* 2 * Copyright (c) 2009-2014, 2016-2019 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 327 unchanged lines hidden (view full) --- 336 || (have_el2 337 && !isSecureBelowEL3(tc) && hcr.rw == 0)); 338 339 // Only know if EL0 using AArch32 from PSTATE 340 if (el == EL0 && !aarch32_at_el1) { 341 // EL0 controlled by PSTATE 342 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 343 |
| 344 known = (cpsr.el == EL0); | 344 known = (currEL(tc) == EL0); |
| 345 aarch32 = (cpsr.width == 1); 346 } else { 347 known = true; 348 aarch32 = (aarch32_below_el3 && el != EL3) 349 || (aarch32_at_el1 && (el == EL0 || el == EL1) ); 350 } 351 } 352 --- 530 unchanged lines hidden --- | 345 aarch32 = (cpsr.width == 1); 346 } else { 347 known = true; 348 aarch32 = (aarch32_below_el3 && el != EL3) 349 || (aarch32_at_el1 && (el == EL0 || el == EL1) ); 350 } 351 } 352 --- 530 unchanged lines hidden --- |