utility.cc (13550:976591c112bc) utility.cc (13585:9c8328ccb03f)
1/*
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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200
201bool
202longDescFormatInUse(ThreadContext *tc)
203{
204 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
205 return ArmSystem::haveLPAE(tc) && ttbcr.eae;
206}
207
1/*
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 191 unchanged lines hidden (view full) ---

200
201bool
202longDescFormatInUse(ThreadContext *tc)
203{
204 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
205 return ArmSystem::haveLPAE(tc) && ttbcr.eae;
206}
207
208MiscReg
208RegVal
209readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
210{
211 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
212 const ExceptionLevel current_el =
213 opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
214
215 const bool is_secure = isSecureBelowEL3(tc);
216

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230 case EL2:
231 case EL3:
232 return getMPIDR(arm_sys, tc);
233 default:
234 panic("Invalid EL for reading MPIDR register\n");
235 }
236}
237
209readMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
210{
211 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
212 const ExceptionLevel current_el =
213 opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
214
215 const bool is_secure = isSecureBelowEL3(tc);
216

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230 case EL2:
231 case EL3:
232 return getMPIDR(arm_sys, tc);
233 default:
234 panic("Invalid EL for reading MPIDR register\n");
235 }
236}
237
238MiscReg
238RegVal
239getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
240{
241 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
242 // Reference Manual
243 //
244 // bit 31 - Multi-processor extensions available
245 // bit 30 - Uni-processor system
246 // bit 24 - Multi-threaded cores

--- 593 unchanged lines hidden --- 		239getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
240{
241 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
242 // Reference Manual
243 //
244 // bit 31 - Multi-processor extensions available
245 // bit 30 - Uni-processor system
246 // bit 24 - Multi-threaded cores

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