utility.cc (13363:15eae7ca2bfd) utility.cc (13364:055bf0fa0f02)
1/*
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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621 break;
622 }
623 }
624 }
625 return trapToHype;
626}
627
628bool
1/*
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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621 break;
622 }
623 }
624 }
625 return trapToHype;
626}
627
628bool
629msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
630 CPACR cpacr /* CPACR_EL1 */)
631{
632 bool trapToSup = false;
633 switch (miscReg) {
634 case MISCREG_FPCR:
635 case MISCREG_FPSR:
636 case MISCREG_FPEXC32_EL2:
637 if ((el == EL0 && cpacr.fpen != 0x3) ||
638 (el == EL1 && !(cpacr.fpen & 0x1)))
639 trapToSup = true;
640 break;
641 default:
642 break;
643 }
644 return trapToSup;
645}
646
647bool
648msrMrs64TrapToHyp(const MiscRegIndex miscReg,
649 ExceptionLevel el,
650 bool isRead,
651 CPTR cptr /* CPTR_EL2 */,
652 HCR hcr /* HCR_EL2 */,
653 SCR scr,
654 CPSR cpsr,
655 bool * isVfpNeon)
656{
657 bool trapToHyp = false;
658 *isVfpNeon = false;
659
660 if (!inSecureState(scr, cpsr) && (el != EL2)) {
661 switch (miscReg) {
662 // FP/SIMD regs
663 case MISCREG_FPCR:
664 case MISCREG_FPSR:
665 case MISCREG_FPEXC32_EL2:
666 trapToHyp = cptr.tfp;
667 *isVfpNeon = true;
668 break;
669 // CPACR
670 case MISCREG_CPACR_EL1:
671 trapToHyp = cptr.tcpac && el == EL1;
672 break;
673 // Virtual memory control regs
674 case MISCREG_SCTLR_EL1:
675 case MISCREG_TTBR0_EL1:
676 case MISCREG_TTBR1_EL1:
677 case MISCREG_TCR_EL1:
678 case MISCREG_ESR_EL1:
679 case MISCREG_FAR_EL1:
680 case MISCREG_AFSR0_EL1:
681 case MISCREG_AFSR1_EL1:
682 case MISCREG_MAIR_EL1:
683 case MISCREG_AMAIR_EL1:
684 case MISCREG_CONTEXTIDR_EL1:
685 trapToHyp = ((hcr.trvm && isRead) || (hcr.tvm && !isRead))
686 && el == EL1;
687 break;
688 // TLB maintenance instructions
689 case MISCREG_TLBI_VMALLE1:
690 case MISCREG_TLBI_VAE1_Xt:
691 case MISCREG_TLBI_ASIDE1_Xt:
692 case MISCREG_TLBI_VAAE1_Xt:
693 case MISCREG_TLBI_VALE1_Xt:
694 case MISCREG_TLBI_VAALE1_Xt:
695 case MISCREG_TLBI_VMALLE1IS:
696 case MISCREG_TLBI_VAE1IS_Xt:
697 case MISCREG_TLBI_ASIDE1IS_Xt:
698 case MISCREG_TLBI_VAAE1IS_Xt:
699 case MISCREG_TLBI_VALE1IS_Xt:
700 case MISCREG_TLBI_VAALE1IS_Xt:
701 trapToHyp = hcr.ttlb && el == EL1;
702 break;
703 // Cache maintenance instructions to the point of unification
704 case MISCREG_IC_IVAU_Xt:
705 case MISCREG_ICIALLU:
706 case MISCREG_ICIALLUIS:
707 case MISCREG_DC_CVAU_Xt:
708 trapToHyp = hcr.tpu && el <= EL1;
709 break;
710 // Data/Unified cache maintenance instructions to the
711 // point of coherency
712 case MISCREG_DC_IVAC_Xt:
713 case MISCREG_DC_CIVAC_Xt:
714 case MISCREG_DC_CVAC_Xt:
715 trapToHyp = hcr.tpc && el <= EL1;
716 break;
717 // Data/Unified cache maintenance instructions by set/way
718 case MISCREG_DC_ISW_Xt:
719 case MISCREG_DC_CSW_Xt:
720 case MISCREG_DC_CISW_Xt:
721 trapToHyp = hcr.tsw && el == EL1;
722 break;
723 // ACTLR
724 case MISCREG_ACTLR_EL1:
725 trapToHyp = hcr.tacr && el == EL1;
726 break;
727
728 // @todo: Trap implementation-dependent functionality based on
729 // hcr.tidcp
730
731 // ID regs, group 3
732 case MISCREG_ID_PFR0_EL1:
733 case MISCREG_ID_PFR1_EL1:
734 case MISCREG_ID_DFR0_EL1:
735 case MISCREG_ID_AFR0_EL1:
736 case MISCREG_ID_MMFR0_EL1:
737 case MISCREG_ID_MMFR1_EL1:
738 case MISCREG_ID_MMFR2_EL1:
739 case MISCREG_ID_MMFR3_EL1:
740 case MISCREG_ID_ISAR0_EL1:
741 case MISCREG_ID_ISAR1_EL1:
742 case MISCREG_ID_ISAR2_EL1:
743 case MISCREG_ID_ISAR3_EL1:
744 case MISCREG_ID_ISAR4_EL1:
745 case MISCREG_ID_ISAR5_EL1:
746 case MISCREG_MVFR0_EL1:
747 case MISCREG_MVFR1_EL1:
748 case MISCREG_MVFR2_EL1:
749 case MISCREG_ID_AA64PFR0_EL1:
750 case MISCREG_ID_AA64PFR1_EL1:
751 case MISCREG_ID_AA64DFR0_EL1:
752 case MISCREG_ID_AA64DFR1_EL1:
753 case MISCREG_ID_AA64ISAR0_EL1:
754 case MISCREG_ID_AA64ISAR1_EL1:
755 case MISCREG_ID_AA64MMFR0_EL1:
756 case MISCREG_ID_AA64MMFR1_EL1:
757 case MISCREG_ID_AA64MMFR2_EL1:
758 case MISCREG_ID_AA64AFR0_EL1:
759 case MISCREG_ID_AA64AFR1_EL1:
760 assert(isRead);
761 trapToHyp = hcr.tid3 && el == EL1;
762 break;
763 // ID regs, group 2
764 case MISCREG_CTR_EL0:
765 case MISCREG_CCSIDR_EL1:
766 case MISCREG_CLIDR_EL1:
767 case MISCREG_CSSELR_EL1:
768 trapToHyp = hcr.tid2 && el <= EL1;
769 break;
770 // ID regs, group 1
771 case MISCREG_AIDR_EL1:
772 case MISCREG_REVIDR_EL1:
773 assert(isRead);
774 trapToHyp = hcr.tid1 && el == EL1;
775 break;
776 default:
777 break;
778 }
779 }
780 return trapToHyp;
781}
782
783bool
784msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr /* CPTR_EL3 */,
785 ExceptionLevel el, bool * isVfpNeon)
786{
787 bool trapToMon = false;
788 *isVfpNeon = false;
789
790 switch (miscReg) {
791 // FP/SIMD regs
792 case MISCREG_FPCR:
793 case MISCREG_FPSR:
794 case MISCREG_FPEXC32_EL2:
795 trapToMon = cptr.tfp;
796 *isVfpNeon = true;
797 break;
798 // CPACR, CPTR
799 case MISCREG_CPACR_EL1:
800 if (el == EL1 || el == EL2) {
801 trapToMon = cptr.tcpac;
802 }
803 break;
804 case MISCREG_CPTR_EL2:
805 if (el == EL2) {
806 trapToMon = cptr.tcpac;
807 }
808 break;
809 default:
810 break;
811 }
812 return trapToMon;
813}
814
815bool
816decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
817 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
818{
819 OperatingMode mode = MODE_UNDEFINED;
820 bool ok = true;
821
822 // R mostly indicates if its a int register or a misc reg, we override
823 // below if the few corner cases

--- 173 unchanged lines hidden --- 		629decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
630 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
631{
632 OperatingMode mode = MODE_UNDEFINED;
633 bool ok = true;
634
635 // R mostly indicates if its a int register or a misc reg, we override
636 // below if the few corner cases

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