utility.cc (13361:f70518db0f0a) | utility.cc (13363:15eae7ca2bfd) |
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1/* 2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 636 unchanged lines hidden (view full) --- 645} 646 647bool 648msrMrs64TrapToHyp(const MiscRegIndex miscReg, 649 ExceptionLevel el, 650 bool isRead, 651 CPTR cptr /* CPTR_EL2 */, 652 HCR hcr /* HCR_EL2 */, | 1/* 2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 636 unchanged lines hidden (view full) --- 645} 646 647bool 648msrMrs64TrapToHyp(const MiscRegIndex miscReg, 649 ExceptionLevel el, 650 bool isRead, 651 CPTR cptr /* CPTR_EL2 */, 652 HCR hcr /* HCR_EL2 */, |
653 SCR scr, 654 CPSR cpsr, |
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653 bool * isVfpNeon) 654{ 655 bool trapToHyp = false; 656 *isVfpNeon = false; 657 | 655 bool * isVfpNeon) 656{ 657 bool trapToHyp = false; 658 *isVfpNeon = false; 659 |
658 switch (miscReg) { 659 // FP/SIMD regs 660 case MISCREG_FPCR: 661 case MISCREG_FPSR: 662 case MISCREG_FPEXC32_EL2: 663 trapToHyp = cptr.tfp; 664 *isVfpNeon = true; 665 break; 666 // CPACR 667 case MISCREG_CPACR_EL1: 668 trapToHyp = cptr.tcpac && el == EL1; 669 break; 670 // Virtual memory control regs 671 case MISCREG_SCTLR_EL1: 672 case MISCREG_TTBR0_EL1: 673 case MISCREG_TTBR1_EL1: 674 case MISCREG_TCR_EL1: 675 case MISCREG_ESR_EL1: 676 case MISCREG_FAR_EL1: 677 case MISCREG_AFSR0_EL1: 678 case MISCREG_AFSR1_EL1: 679 case MISCREG_MAIR_EL1: 680 case MISCREG_AMAIR_EL1: 681 case MISCREG_CONTEXTIDR_EL1: 682 trapToHyp = ((hcr.trvm && isRead) || (hcr.tvm && !isRead)) 683 && el == EL1; 684 break; 685 // TLB maintenance instructions 686 case MISCREG_TLBI_VMALLE1: 687 case MISCREG_TLBI_VAE1_Xt: 688 case MISCREG_TLBI_ASIDE1_Xt: 689 case MISCREG_TLBI_VAAE1_Xt: 690 case MISCREG_TLBI_VALE1_Xt: 691 case MISCREG_TLBI_VAALE1_Xt: 692 case MISCREG_TLBI_VMALLE1IS: 693 case MISCREG_TLBI_VAE1IS_Xt: 694 case MISCREG_TLBI_ASIDE1IS_Xt: 695 case MISCREG_TLBI_VAAE1IS_Xt: 696 case MISCREG_TLBI_VALE1IS_Xt: 697 case MISCREG_TLBI_VAALE1IS_Xt: 698 trapToHyp = hcr.ttlb && el == EL1; 699 break; 700 // Cache maintenance instructions to the point of unification 701 case MISCREG_IC_IVAU_Xt: 702 case MISCREG_ICIALLU: 703 case MISCREG_ICIALLUIS: 704 case MISCREG_DC_CVAU_Xt: 705 trapToHyp = hcr.tpu && el <= EL1; 706 break; 707 // Data/Unified cache maintenance instructions to the point of coherency 708 case MISCREG_DC_IVAC_Xt: 709 case MISCREG_DC_CIVAC_Xt: 710 case MISCREG_DC_CVAC_Xt: 711 trapToHyp = hcr.tpc && el <= EL1; 712 break; 713 // Data/Unified cache maintenance instructions by set/way 714 case MISCREG_DC_ISW_Xt: 715 case MISCREG_DC_CSW_Xt: 716 case MISCREG_DC_CISW_Xt: 717 trapToHyp = hcr.tsw && el == EL1; 718 break; 719 // ACTLR 720 case MISCREG_ACTLR_EL1: 721 trapToHyp = hcr.tacr && el == EL1; 722 break; | 660 if (!inSecureState(scr, cpsr) && (el != EL2)) { 661 switch (miscReg) { 662 // FP/SIMD regs 663 case MISCREG_FPCR: 664 case MISCREG_FPSR: 665 case MISCREG_FPEXC32_EL2: 666 trapToHyp = cptr.tfp; 667 *isVfpNeon = true; 668 break; 669 // CPACR 670 case MISCREG_CPACR_EL1: 671 trapToHyp = cptr.tcpac && el == EL1; 672 break; 673 // Virtual memory control regs 674 case MISCREG_SCTLR_EL1: 675 case MISCREG_TTBR0_EL1: 676 case MISCREG_TTBR1_EL1: 677 case MISCREG_TCR_EL1: 678 case MISCREG_ESR_EL1: 679 case MISCREG_FAR_EL1: 680 case MISCREG_AFSR0_EL1: 681 case MISCREG_AFSR1_EL1: 682 case MISCREG_MAIR_EL1: 683 case MISCREG_AMAIR_EL1: 684 case MISCREG_CONTEXTIDR_EL1: 685 trapToHyp = ((hcr.trvm && isRead) || (hcr.tvm && !isRead)) 686 && el == EL1; 687 break; 688 // TLB maintenance instructions 689 case MISCREG_TLBI_VMALLE1: 690 case MISCREG_TLBI_VAE1_Xt: 691 case MISCREG_TLBI_ASIDE1_Xt: 692 case MISCREG_TLBI_VAAE1_Xt: 693 case MISCREG_TLBI_VALE1_Xt: 694 case MISCREG_TLBI_VAALE1_Xt: 695 case MISCREG_TLBI_VMALLE1IS: 696 case MISCREG_TLBI_VAE1IS_Xt: 697 case MISCREG_TLBI_ASIDE1IS_Xt: 698 case MISCREG_TLBI_VAAE1IS_Xt: 699 case MISCREG_TLBI_VALE1IS_Xt: 700 case MISCREG_TLBI_VAALE1IS_Xt: 701 trapToHyp = hcr.ttlb && el == EL1; 702 break; 703 // Cache maintenance instructions to the point of unification 704 case MISCREG_IC_IVAU_Xt: 705 case MISCREG_ICIALLU: 706 case MISCREG_ICIALLUIS: 707 case MISCREG_DC_CVAU_Xt: 708 trapToHyp = hcr.tpu && el <= EL1; 709 break; 710 // Data/Unified cache maintenance instructions to the 711 // point of coherency 712 case MISCREG_DC_IVAC_Xt: 713 case MISCREG_DC_CIVAC_Xt: 714 case MISCREG_DC_CVAC_Xt: 715 trapToHyp = hcr.tpc && el <= EL1; 716 break; 717 // Data/Unified cache maintenance instructions by set/way 718 case MISCREG_DC_ISW_Xt: 719 case MISCREG_DC_CSW_Xt: 720 case MISCREG_DC_CISW_Xt: 721 trapToHyp = hcr.tsw && el == EL1; 722 break; 723 // ACTLR 724 case MISCREG_ACTLR_EL1: 725 trapToHyp = hcr.tacr && el == EL1; 726 break; |
723 | 727 |
724 // @todo: Trap implementation-dependent functionality based on 725 // hcr.tidcp | 728 // @todo: Trap implementation-dependent functionality based on 729 // hcr.tidcp |
726 | 730 |
727 // ID regs, group 3 728 case MISCREG_ID_PFR0_EL1: 729 case MISCREG_ID_PFR1_EL1: 730 case MISCREG_ID_DFR0_EL1: 731 case MISCREG_ID_AFR0_EL1: 732 case MISCREG_ID_MMFR0_EL1: 733 case MISCREG_ID_MMFR1_EL1: 734 case MISCREG_ID_MMFR2_EL1: 735 case MISCREG_ID_MMFR3_EL1: 736 case MISCREG_ID_ISAR0_EL1: 737 case MISCREG_ID_ISAR1_EL1: 738 case MISCREG_ID_ISAR2_EL1: 739 case MISCREG_ID_ISAR3_EL1: 740 case MISCREG_ID_ISAR4_EL1: 741 case MISCREG_ID_ISAR5_EL1: 742 case MISCREG_MVFR0_EL1: 743 case MISCREG_MVFR1_EL1: 744 case MISCREG_MVFR2_EL1: 745 case MISCREG_ID_AA64PFR0_EL1: 746 case MISCREG_ID_AA64PFR1_EL1: 747 case MISCREG_ID_AA64DFR0_EL1: 748 case MISCREG_ID_AA64DFR1_EL1: 749 case MISCREG_ID_AA64ISAR0_EL1: 750 case MISCREG_ID_AA64ISAR1_EL1: 751 case MISCREG_ID_AA64MMFR0_EL1: 752 case MISCREG_ID_AA64MMFR1_EL1: 753 case MISCREG_ID_AA64MMFR2_EL1: 754 case MISCREG_ID_AA64AFR0_EL1: 755 case MISCREG_ID_AA64AFR1_EL1: 756 assert(isRead); 757 trapToHyp = hcr.tid3 && el == EL1; 758 break; 759 // ID regs, group 2 760 case MISCREG_CTR_EL0: 761 case MISCREG_CCSIDR_EL1: 762 case MISCREG_CLIDR_EL1: 763 case MISCREG_CSSELR_EL1: 764 trapToHyp = hcr.tid2 && el <= EL1; 765 break; 766 // ID regs, group 1 767 case MISCREG_AIDR_EL1: 768 case MISCREG_REVIDR_EL1: 769 assert(isRead); 770 trapToHyp = hcr.tid1 && el == EL1; 771 break; 772 default: 773 break; | 731 // ID regs, group 3 732 case MISCREG_ID_PFR0_EL1: 733 case MISCREG_ID_PFR1_EL1: 734 case MISCREG_ID_DFR0_EL1: 735 case MISCREG_ID_AFR0_EL1: 736 case MISCREG_ID_MMFR0_EL1: 737 case MISCREG_ID_MMFR1_EL1: 738 case MISCREG_ID_MMFR2_EL1: 739 case MISCREG_ID_MMFR3_EL1: 740 case MISCREG_ID_ISAR0_EL1: 741 case MISCREG_ID_ISAR1_EL1: 742 case MISCREG_ID_ISAR2_EL1: 743 case MISCREG_ID_ISAR3_EL1: 744 case MISCREG_ID_ISAR4_EL1: 745 case MISCREG_ID_ISAR5_EL1: 746 case MISCREG_MVFR0_EL1: 747 case MISCREG_MVFR1_EL1: 748 case MISCREG_MVFR2_EL1: 749 case MISCREG_ID_AA64PFR0_EL1: 750 case MISCREG_ID_AA64PFR1_EL1: 751 case MISCREG_ID_AA64DFR0_EL1: 752 case MISCREG_ID_AA64DFR1_EL1: 753 case MISCREG_ID_AA64ISAR0_EL1: 754 case MISCREG_ID_AA64ISAR1_EL1: 755 case MISCREG_ID_AA64MMFR0_EL1: 756 case MISCREG_ID_AA64MMFR1_EL1: 757 case MISCREG_ID_AA64MMFR2_EL1: 758 case MISCREG_ID_AA64AFR0_EL1: 759 case MISCREG_ID_AA64AFR1_EL1: 760 assert(isRead); 761 trapToHyp = hcr.tid3 && el == EL1; 762 break; 763 // ID regs, group 2 764 case MISCREG_CTR_EL0: 765 case MISCREG_CCSIDR_EL1: 766 case MISCREG_CLIDR_EL1: 767 case MISCREG_CSSELR_EL1: 768 trapToHyp = hcr.tid2 && el <= EL1; 769 break; 770 // ID regs, group 1 771 case MISCREG_AIDR_EL1: 772 case MISCREG_REVIDR_EL1: 773 assert(isRead); 774 trapToHyp = hcr.tid1 && el == EL1; 775 break; 776 default: 777 break; 778 } |
774 } 775 return trapToHyp; 776} 777 778bool 779msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr /* CPTR_EL3 */, 780 ExceptionLevel el, bool * isVfpNeon) 781{ --- 210 unchanged lines hidden --- | 779 } 780 return trapToHyp; 781} 782 783bool 784msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr /* CPTR_EL3 */, 785 ExceptionLevel el, bool * isVfpNeon) 786{ --- 210 unchanged lines hidden --- |