1/* 2 * Copyright (c) 2009-2014, 2016-2019 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 211 unchanged lines hidden (view full) --- 220{ 221 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR); 222 return ArmSystem::haveLPAE(tc) && ttbcr.eae; 223} 224 225RegVal 226readMPIDR(ArmSystem *arm_sys, ThreadContext *tc) 227{ |
228 const ExceptionLevel current_el = currEL(tc); |
229 230 const bool is_secure = isSecureBelowEL3(tc); 231 232 switch (current_el) { 233 case EL0: 234 // Note: in MsrMrs instruction we read the register value before 235 // checking access permissions. This means that EL0 entry must 236 // be part of the table even if MPIDR is not accessible in user --- 112 unchanged lines hidden (view full) --- 349 } 350 351 return std::make_pair(known, aarch32); 352} 353 354bool 355isBigEndian64(ThreadContext *tc) 356{ |
357 switch (currEL(tc)) { |
358 case EL3: 359 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee; 360 case EL2: 361 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee; 362 case EL1: 363 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee; 364 case EL0: 365 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e; --- 447 unchanged lines hidden (view full) --- 813 } 814 } 815 return (ok); 816} 817 818bool 819SPAlignmentCheckEnabled(ThreadContext* tc) 820{ |
821 switch (currEL(tc)) { |
822 case EL3: 823 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa; 824 case EL2: 825 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa; 826 case EL1: 827 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa; 828 case EL0: 829 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0; --- 51 unchanged lines hidden --- |