1/*
2 * Copyright (c) 2009-2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
43#include "arch/arm/tlb.hh"
44#include "arch/arm/utility.hh"
45#include "arch/arm/vtophys.hh"
46#include "cpu/checker/cpu.hh"
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "mem/fs_translating_port_proxy.hh"
50#include "sim/full_system.hh"
51
52namespace ArmISA {
53
54void
55initCPU(ThreadContext *tc, int cpuId)
56{
57 // Reset CP15?? What does that mean -- ali
58
59 // FPEXC.EN = 0
60
61 static Fault reset = new Reset;
62 reset->invoke(tc);
63}
64
65uint64_t
66getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
67{
68 if (!FullSystem) {
69 panic("getArgument() only implemented for full system mode.\n");
70 M5_DUMMY_RETURN
71 }
72
73 if (size == (uint16_t)(-1))
74 size = ArmISA::MachineBytes;
75 if (fp)
76 panic("getArgument(): Floating point arguments not implemented\n");
77
78 if (number < NumArgumentRegs) {
79 // If the argument is 64 bits, it must be in an even regiser
80 // number. Increment the number here if it isn't even.
81 if (size == sizeof(uint64_t)) {
82 if ((number % 2) != 0)
83 number++;
84 // Read the two halves of the data. Number is inc here to
85 // get the second half of the 64 bit reg.
86 uint64_t tmp;
87 tmp = tc->readIntReg(number++);
88 tmp |= tc->readIntReg(number) << 32;
89 return tmp;
90 } else {
91 return tc->readIntReg(number);
92 }
93 } else {
94 Addr sp = tc->readIntReg(StackPointerReg);
95 FSTranslatingPortProxy &vp = tc->getVirtProxy();
96 uint64_t arg;
97 if (size == sizeof(uint64_t)) {
98 // If the argument is even it must be aligned
99 if ((number % 2) != 0)
100 number++;
101 arg = vp.read<uint64_t>(sp +
102 (number-NumArgumentRegs) * sizeof(uint32_t));
103 // since two 32 bit args == 1 64 bit arg, increment number
104 number++;
105 } else {
106 arg = vp.read<uint32_t>(sp +
107 (number-NumArgumentRegs) * sizeof(uint32_t));
108 }
109 return arg;
110 }
111}
112
113void
114skipFunction(ThreadContext *tc)
115{
| 1/*
2 * Copyright (c) 2009-2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
43#include "arch/arm/tlb.hh"
44#include "arch/arm/utility.hh"
45#include "arch/arm/vtophys.hh"
46#include "cpu/checker/cpu.hh"
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "mem/fs_translating_port_proxy.hh"
50#include "sim/full_system.hh"
51
52namespace ArmISA {
53
54void
55initCPU(ThreadContext *tc, int cpuId)
56{
57 // Reset CP15?? What does that mean -- ali
58
59 // FPEXC.EN = 0
60
61 static Fault reset = new Reset;
62 reset->invoke(tc);
63}
64
65uint64_t
66getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
67{
68 if (!FullSystem) {
69 panic("getArgument() only implemented for full system mode.\n");
70 M5_DUMMY_RETURN
71 }
72
73 if (size == (uint16_t)(-1))
74 size = ArmISA::MachineBytes;
75 if (fp)
76 panic("getArgument(): Floating point arguments not implemented\n");
77
78 if (number < NumArgumentRegs) {
79 // If the argument is 64 bits, it must be in an even regiser
80 // number. Increment the number here if it isn't even.
81 if (size == sizeof(uint64_t)) {
82 if ((number % 2) != 0)
83 number++;
84 // Read the two halves of the data. Number is inc here to
85 // get the second half of the 64 bit reg.
86 uint64_t tmp;
87 tmp = tc->readIntReg(number++);
88 tmp |= tc->readIntReg(number) << 32;
89 return tmp;
90 } else {
91 return tc->readIntReg(number);
92 }
93 } else {
94 Addr sp = tc->readIntReg(StackPointerReg);
95 FSTranslatingPortProxy &vp = tc->getVirtProxy();
96 uint64_t arg;
97 if (size == sizeof(uint64_t)) {
98 // If the argument is even it must be aligned
99 if ((number % 2) != 0)
100 number++;
101 arg = vp.read<uint64_t>(sp +
102 (number-NumArgumentRegs) * sizeof(uint32_t));
103 // since two 32 bit args == 1 64 bit arg, increment number
104 number++;
105 } else {
106 arg = vp.read<uint32_t>(sp +
107 (number-NumArgumentRegs) * sizeof(uint32_t));
108 }
109 return arg;
110 }
111}
112
113void
114skipFunction(ThreadContext *tc)
115{
|
137 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
138
139 // setMiscReg "with effect" will set the misc register mapping correctly.
140 // e.g. updateRegMap(val)
141 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
142
143 // Copy over the PC State
144 dest->pcState(src->pcState());
145
146 // Invalidate the tlb misc register cache
147 dest->getITBPtr()->invalidateMiscReg();
148 dest->getDTBPtr()->invalidateMiscReg();
149}
150
151Addr
152truncPage(Addr addr)
153{
154 return addr & ~(PageBytes - 1);
155}
156
157Addr
158roundPage(Addr addr)
159{
160 return (addr + PageBytes - 1) & ~(PageBytes - 1);
161}
162
163} // namespace ArmISA
| 140 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
141
142 // setMiscReg "with effect" will set the misc register mapping correctly.
143 // e.g. updateRegMap(val)
144 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
145
146 // Copy over the PC State
147 dest->pcState(src->pcState());
148
149 // Invalidate the tlb misc register cache
150 dest->getITBPtr()->invalidateMiscReg();
151 dest->getDTBPtr()->invalidateMiscReg();
152}
153
154Addr
155truncPage(Addr addr)
156{
157 return addr & ~(PageBytes - 1);
158}
159
160Addr
161roundPage(Addr addr)
162{
163 return (addr + PageBytes - 1) & ~(PageBytes - 1);
164}
165
166} // namespace ArmISA
|