1/*
2 * Copyright (c) 2009-2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
43#include "arch/arm/tlb.hh"
44#include "arch/arm/utility.hh"
45#include "arch/arm/vtophys.hh"
46#include "cpu/thread_context.hh"
47#include "mem/fs_translating_port_proxy.hh"
48#include "sim/full_system.hh"
49
50namespace ArmISA {
51
52void
53initCPU(ThreadContext *tc, int cpuId)
54{
55 // Reset CP15?? What does that mean -- ali
56
57 // FPEXC.EN = 0
58
59 static Fault reset = new Reset;
60 reset->invoke(tc);
61}
62
63uint64_t
64getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
65{
| 1/*
2 * Copyright (c) 2009-2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
43#include "arch/arm/tlb.hh"
44#include "arch/arm/utility.hh"
45#include "arch/arm/vtophys.hh"
46#include "cpu/thread_context.hh"
47#include "mem/fs_translating_port_proxy.hh"
48#include "sim/full_system.hh"
49
50namespace ArmISA {
51
52void
53initCPU(ThreadContext *tc, int cpuId)
54{
55 // Reset CP15?? What does that mean -- ali
56
57 // FPEXC.EN = 0
58
59 static Fault reset = new Reset;
60 reset->invoke(tc);
61}
62
63uint64_t
64getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
65{
|
66 if (FullSystem) {
67 if (size == (uint16_t)(-1))
68 size = ArmISA::MachineBytes;
69 if (fp)
70 panic("getArgument(): Floating point arguments not implemented\n");
| 66 if (!FullSystem) {
67 panic("getArgument() only implemented for full system mode.\n");
68 M5_DUMMY_RETURN
69 }
|
71
| 70
|
72 if (number < NumArgumentRegs) {
73 // If the argument is 64 bits, it must be in an even regiser
74 // number. Increment the number here if it isn't even.
75 if (size == sizeof(uint64_t)) {
76 if ((number % 2) != 0)
77 number++;
78 // Read the two halves of the data. Number is inc here to
79 // get the second half of the 64 bit reg.
80 uint64_t tmp;
81 tmp = tc->readIntReg(number++);
82 tmp |= tc->readIntReg(number) << 32;
83 return tmp;
84 } else {
85 return tc->readIntReg(number);
86 }
87 } else {
88 Addr sp = tc->readIntReg(StackPointerReg);
89 FSTranslatingPortProxy* vp = tc->getVirtProxy();
90 uint64_t arg;
91 if (size == sizeof(uint64_t)) {
92 // If the argument is even it must be aligned
93 if ((number % 2) != 0)
94 number++;
95 arg = vp->read<uint64_t>(sp +
96 (number-NumArgumentRegs) * sizeof(uint32_t));
97 // since two 32 bit args == 1 64 bit arg, increment number
| 71 if (size == (uint16_t)(-1))
72 size = ArmISA::MachineBytes;
73 if (fp)
74 panic("getArgument(): Floating point arguments not implemented\n");
75
76 if (number < NumArgumentRegs) {
77 // If the argument is 64 bits, it must be in an even regiser
78 // number. Increment the number here if it isn't even.
79 if (size == sizeof(uint64_t)) {
80 if ((number % 2) != 0)
|
98 number++;
| 81 number++;
|
99 } else {
100 arg = vp->read<uint32_t>(sp +
101 (number-NumArgumentRegs) * sizeof(uint32_t));
102 }
103 return arg;
| 82 // Read the two halves of the data. Number is inc here to
83 // get the second half of the 64 bit reg.
84 uint64_t tmp;
85 tmp = tc->readIntReg(number++);
86 tmp |= tc->readIntReg(number) << 32;
87 return tmp;
88 } else {
89 return tc->readIntReg(number);
|
104 }
105 } else {
| 90 }
91 } else {
|
106 panic("getArgument() only implemented for full system mode.\n");
107 M5_DUMMY_RETURN
| 92 Addr sp = tc->readIntReg(StackPointerReg);
93 FSTranslatingPortProxy* vp = tc->getVirtProxy();
94 uint64_t arg;
95 if (size == sizeof(uint64_t)) {
96 // If the argument is even it must be aligned
97 if ((number % 2) != 0)
98 number++;
99 arg = vp->read<uint64_t>(sp +
100 (number-NumArgumentRegs) * sizeof(uint32_t));
101 // since two 32 bit args == 1 64 bit arg, increment number
102 number++;
103 } else {
104 arg = vp->read<uint32_t>(sp +
105 (number-NumArgumentRegs) * sizeof(uint32_t));
106 }
107 return arg;
|
108 }
109}
110
111void
112skipFunction(ThreadContext *tc)
113{
114 TheISA::PCState newPC = tc->pcState();
115 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
116 tc->pcState(newPC);
117}
118
119void
120copyRegs(ThreadContext *src, ThreadContext *dest)
121{
122 int i;
123
124 int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode;
125
126 // Make sure we're in user mode, so we can easily see all the registers
127 // in the copy loop
128 src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
129 dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
130
131 for(i = 0; i < TheISA::NumIntRegs; i++)
132 dest->setIntReg(i, src->readIntReg(i));
133
134 // Restore us back to the old mode
135 src->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
136 dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
137
138 for(i = 0; i < TheISA::NumFloatRegs; i++)
139 dest->setFloatReg(i, src->readFloatReg(i));
140 for(i = 0; i < TheISA::NumMiscRegs; i++)
141 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
142
143 // setMiscReg "with effect" will set the misc register mapping correctly.
144 // e.g. updateRegMap(val)
145 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
146
147 // Copy over the PC State
148 dest->pcState(src->pcState());
149
150 // Invalidate the tlb misc register cache
151 dest->getITBPtr()->invalidateMiscReg();
152 dest->getDTBPtr()->invalidateMiscReg();
153}
154
155Addr
156truncPage(Addr addr)
157{
158 return addr & ~(PageBytes - 1);
159}
160
161Addr
162roundPage(Addr addr)
163{
164 return (addr + PageBytes - 1) & ~(PageBytes - 1);
165}
166
167} // namespace ArmISA
| 108 }
109}
110
111void
112skipFunction(ThreadContext *tc)
113{
114 TheISA::PCState newPC = tc->pcState();
115 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
116 tc->pcState(newPC);
117}
118
119void
120copyRegs(ThreadContext *src, ThreadContext *dest)
121{
122 int i;
123
124 int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode;
125
126 // Make sure we're in user mode, so we can easily see all the registers
127 // in the copy loop
128 src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
129 dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
130
131 for(i = 0; i < TheISA::NumIntRegs; i++)
132 dest->setIntReg(i, src->readIntReg(i));
133
134 // Restore us back to the old mode
135 src->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
136 dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
137
138 for(i = 0; i < TheISA::NumFloatRegs; i++)
139 dest->setFloatReg(i, src->readFloatReg(i));
140 for(i = 0; i < TheISA::NumMiscRegs; i++)
141 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
142
143 // setMiscReg "with effect" will set the misc register mapping correctly.
144 // e.g. updateRegMap(val)
145 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
146
147 // Copy over the PC State
148 dest->pcState(src->pcState());
149
150 // Invalidate the tlb misc register cache
151 dest->getITBPtr()->invalidateMiscReg();
152 dest->getDTBPtr()->invalidateMiscReg();
153}
154
155Addr
156truncPage(Addr addr)
157{
158 return addr & ~(PageBytes - 1);
159}
160
161Addr
162roundPage(Addr addr)
163{
164 return (addr + PageBytes - 1) & ~(PageBytes - 1);
165}
166
167} // namespace ArmISA
|