1/*
2 * Copyright (c) 2009-2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
43#include "arch/arm/utility.hh"
| 1/*
2 * Copyright (c) 2009-2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
43#include "arch/arm/utility.hh"
|
| 44#include "config/use_checker.hh"
|
44#include "cpu/thread_context.hh"
45
46#if FULL_SYSTEM
47#include "arch/arm/vtophys.hh"
48#include "mem/fs_translating_port_proxy.hh"
49#endif
50
51#include "arch/arm/tlb.hh"
52
53namespace ArmISA {
54
55void
56initCPU(ThreadContext *tc, int cpuId)
57{
58 // Reset CP15?? What does that mean -- ali
59
60 // FPEXC.EN = 0
61
62 static Fault reset = new Reset;
63 reset->invoke(tc);
64}
65
66uint64_t
67getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
68{
69#if FULL_SYSTEM
70 if (size == (uint16_t)(-1))
71 size = ArmISA::MachineBytes;
72 if (fp)
73 panic("getArgument(): Floating point arguments not implemented\n");
74
75 if (number < NumArgumentRegs) {
76 // If the argument is 64 bits, it must be in an even regiser number
77 // Increment the number here if it isn't even
78 if (size == sizeof(uint64_t)) {
79 if ((number % 2) != 0)
80 number++;
81 // Read the two halves of the data
82 // number is inc here to get the second half of the 64 bit reg
83 uint64_t tmp;
84 tmp = tc->readIntReg(number++);
85 tmp |= tc->readIntReg(number) << 32;
86 return tmp;
87 } else {
88 return tc->readIntReg(number);
89 }
90 } else {
91 Addr sp = tc->readIntReg(StackPointerReg);
92 FSTranslatingPortProxy* vp = tc->getVirtProxy();
93 uint64_t arg;
94 if (size == sizeof(uint64_t)) {
95 // If the argument is even it must be aligned
96 if ((number % 2) != 0)
97 number++;
98 arg = vp->read<uint64_t>(sp +
99 (number-NumArgumentRegs) * sizeof(uint32_t));
100 // since two 32 bit args == 1 64 bit arg, increment number
101 number++;
102 } else {
103 arg = vp->read<uint32_t>(sp +
104 (number-NumArgumentRegs) * sizeof(uint32_t));
105 }
106 return arg;
107 }
108#else
109 panic("getArgument() only implemented for FULL_SYSTEM\n");
110 M5_DUMMY_RETURN
111#endif
112}
113
114void
115skipFunction(ThreadContext *tc)
116{
117 TheISA::PCState newPC = tc->pcState();
118 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
| 45#include "cpu/thread_context.hh"
46
47#if FULL_SYSTEM
48#include "arch/arm/vtophys.hh"
49#include "mem/fs_translating_port_proxy.hh"
50#endif
51
52#include "arch/arm/tlb.hh"
53
54namespace ArmISA {
55
56void
57initCPU(ThreadContext *tc, int cpuId)
58{
59 // Reset CP15?? What does that mean -- ali
60
61 // FPEXC.EN = 0
62
63 static Fault reset = new Reset;
64 reset->invoke(tc);
65}
66
67uint64_t
68getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
69{
70#if FULL_SYSTEM
71 if (size == (uint16_t)(-1))
72 size = ArmISA::MachineBytes;
73 if (fp)
74 panic("getArgument(): Floating point arguments not implemented\n");
75
76 if (number < NumArgumentRegs) {
77 // If the argument is 64 bits, it must be in an even regiser number
78 // Increment the number here if it isn't even
79 if (size == sizeof(uint64_t)) {
80 if ((number % 2) != 0)
81 number++;
82 // Read the two halves of the data
83 // number is inc here to get the second half of the 64 bit reg
84 uint64_t tmp;
85 tmp = tc->readIntReg(number++);
86 tmp |= tc->readIntReg(number) << 32;
87 return tmp;
88 } else {
89 return tc->readIntReg(number);
90 }
91 } else {
92 Addr sp = tc->readIntReg(StackPointerReg);
93 FSTranslatingPortProxy* vp = tc->getVirtProxy();
94 uint64_t arg;
95 if (size == sizeof(uint64_t)) {
96 // If the argument is even it must be aligned
97 if ((number % 2) != 0)
98 number++;
99 arg = vp->read<uint64_t>(sp +
100 (number-NumArgumentRegs) * sizeof(uint32_t));
101 // since two 32 bit args == 1 64 bit arg, increment number
102 number++;
103 } else {
104 arg = vp->read<uint32_t>(sp +
105 (number-NumArgumentRegs) * sizeof(uint32_t));
106 }
107 return arg;
108 }
109#else
110 panic("getArgument() only implemented for FULL_SYSTEM\n");
111 M5_DUMMY_RETURN
112#endif
113}
114
115void
116skipFunction(ThreadContext *tc)
117{
118 TheISA::PCState newPC = tc->pcState();
119 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
|
| 120#if USE_CHECKER
121 tc->pcStateNoRecord(newPC);
122#else
|
119 tc->pcState(newPC);
| 123 tc->pcState(newPC);
|
| 124#endif
|
120}
121
122void
123copyRegs(ThreadContext *src, ThreadContext *dest)
124{
125 int i;
126
127 int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode;
128
129 // Make sure we're in user mode, so we can easily see all the registers
130 // in the copy loop
131 src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
132 dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
133
134 for(i = 0; i < TheISA::NumIntRegs; i++)
135 dest->setIntReg(i, src->readIntReg(i));
136
137 // Restore us back to the old mode
138 src->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
139 dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
140
141 for(i = 0; i < TheISA::NumFloatRegs; i++)
142 dest->setFloatReg(i, src->readFloatReg(i));
143 for(i = 0; i < TheISA::NumMiscRegs; i++)
144 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
145
146 // setMiscReg "with effect" will set the misc register mapping correctly.
147 // e.g. updateRegMap(val)
148 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
149
150 // Copy over the PC State
151 dest->pcState(src->pcState());
152
153 // Invalidate the tlb misc register cache
154 dest->getITBPtr()->invalidateMiscReg();
155 dest->getDTBPtr()->invalidateMiscReg();
156}
157
158Addr
159truncPage(Addr addr)
160{
161 return addr & ~(PageBytes - 1);
162}
163
164Addr
165roundPage(Addr addr)
166{
167 return (addr + PageBytes - 1) & ~(PageBytes - 1);
168}
169
170} // namespace ArmISA
| 125}
126
127void
128copyRegs(ThreadContext *src, ThreadContext *dest)
129{
130 int i;
131
132 int saved_mode = ((CPSR)src->readMiscReg(MISCREG_CPSR)).mode;
133
134 // Make sure we're in user mode, so we can easily see all the registers
135 // in the copy loop
136 src->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
137 dest->setMiscReg(MISCREG_CPSR_MODE, MODE_USER);
138
139 for(i = 0; i < TheISA::NumIntRegs; i++)
140 dest->setIntReg(i, src->readIntReg(i));
141
142 // Restore us back to the old mode
143 src->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
144 dest->setMiscReg(MISCREG_CPSR_MODE, saved_mode);
145
146 for(i = 0; i < TheISA::NumFloatRegs; i++)
147 dest->setFloatReg(i, src->readFloatReg(i));
148 for(i = 0; i < TheISA::NumMiscRegs; i++)
149 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
150
151 // setMiscReg "with effect" will set the misc register mapping correctly.
152 // e.g. updateRegMap(val)
153 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
154
155 // Copy over the PC State
156 dest->pcState(src->pcState());
157
158 // Invalidate the tlb misc register cache
159 dest->getITBPtr()->invalidateMiscReg();
160 dest->getDTBPtr()->invalidateMiscReg();
161}
162
163Addr
164truncPage(Addr addr)
165{
166 return addr & ~(PageBytes - 1);
167}
168
169Addr
170roundPage(Addr addr)
171{
172 return (addr + PageBytes - 1) & ~(PageBytes - 1);
173}
174
175} // namespace ArmISA
|