1/*
2 * Copyright (c) 2009-2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
43#include "arch/arm/utility.hh"
44#include "cpu/thread_context.hh"
45
46#if FULL_SYSTEM
47#include "arch/arm/vtophys.hh"
48#include "mem/vport.hh"
49#endif
50
51namespace ArmISA {
52
53void
54initCPU(ThreadContext *tc, int cpuId)
55{
56 // Reset CP15?? What does that mean -- ali
57
58 // FPEXC.EN = 0
59
60 static Fault reset = new Reset;
61 if (cpuId == 0)
62 reset->invoke(tc);
63}
64
65uint64_t
66getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
67{
68#if FULL_SYSTEM
69 if (size == (uint16_t)(-1))
70 size = ArmISA::MachineBytes;
71 if (fp)
72 panic("getArgument(): Floating point arguments not implemented\n");
73
74 if (number < NumArgumentRegs) {
75 // If the argument is 64 bits, it must be in an even regiser number
76 // Increment the number here if it isn't even
77 if (size == sizeof(uint64_t)) {
78 if ((number % 2) != 0)
79 number++;
80 // Read the two halves of the data
81 // number is inc here to get the second half of the 64 bit reg
82 uint64_t tmp;
83 tmp = tc->readIntReg(number++);
84 tmp |= tc->readIntReg(number) << 32;
85 return tmp;
86 } else {
87 return tc->readIntReg(number);
88 }
89 } else {
90 Addr sp = tc->readIntReg(StackPointerReg);
91 VirtualPort *vp = tc->getVirtPort();
92 uint64_t arg;
93 if (size == sizeof(uint64_t)) {
94 // If the argument is even it must be aligned
95 if ((number % 2) != 0)
96 number++;
97 arg = vp->read<uint64_t>(sp +
98 (number-NumArgumentRegs) * sizeof(uint32_t));
99 // since two 32 bit args == 1 64 bit arg, increment number
100 number++;
101 } else {
102 arg = vp->read<uint32_t>(sp +
103 (number-NumArgumentRegs) * sizeof(uint32_t));
104 }
105 return arg;
106 }
107#else
108 panic("getArgument() only implemented for FULL_SYSTEM\n");
109 M5_DUMMY_RETURN
110#endif
111}
112
113Fault
114setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2)
115{
116 return new UnimpFault(csprintf("MCR CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n",
117 CRn, opc1, CRm, opc2));
118}
119
120Fault
121readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2)
122{
123 return new UnimpFault(csprintf("MRC CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n",
124 CRn, opc1, CRm, opc2));
125
126}
127
128void
129skipFunction(ThreadContext *tc)
130{
131 TheISA::PCState newPC = tc->pcState();
132 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
133 tc->pcState(newPC);
134}
135
| 1/*
2 * Copyright (c) 2009-2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40
41#include "arch/arm/faults.hh"
42#include "arch/arm/isa_traits.hh"
43#include "arch/arm/utility.hh"
44#include "cpu/thread_context.hh"
45
46#if FULL_SYSTEM
47#include "arch/arm/vtophys.hh"
48#include "mem/vport.hh"
49#endif
50
51namespace ArmISA {
52
53void
54initCPU(ThreadContext *tc, int cpuId)
55{
56 // Reset CP15?? What does that mean -- ali
57
58 // FPEXC.EN = 0
59
60 static Fault reset = new Reset;
61 if (cpuId == 0)
62 reset->invoke(tc);
63}
64
65uint64_t
66getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
67{
68#if FULL_SYSTEM
69 if (size == (uint16_t)(-1))
70 size = ArmISA::MachineBytes;
71 if (fp)
72 panic("getArgument(): Floating point arguments not implemented\n");
73
74 if (number < NumArgumentRegs) {
75 // If the argument is 64 bits, it must be in an even regiser number
76 // Increment the number here if it isn't even
77 if (size == sizeof(uint64_t)) {
78 if ((number % 2) != 0)
79 number++;
80 // Read the two halves of the data
81 // number is inc here to get the second half of the 64 bit reg
82 uint64_t tmp;
83 tmp = tc->readIntReg(number++);
84 tmp |= tc->readIntReg(number) << 32;
85 return tmp;
86 } else {
87 return tc->readIntReg(number);
88 }
89 } else {
90 Addr sp = tc->readIntReg(StackPointerReg);
91 VirtualPort *vp = tc->getVirtPort();
92 uint64_t arg;
93 if (size == sizeof(uint64_t)) {
94 // If the argument is even it must be aligned
95 if ((number % 2) != 0)
96 number++;
97 arg = vp->read<uint64_t>(sp +
98 (number-NumArgumentRegs) * sizeof(uint32_t));
99 // since two 32 bit args == 1 64 bit arg, increment number
100 number++;
101 } else {
102 arg = vp->read<uint32_t>(sp +
103 (number-NumArgumentRegs) * sizeof(uint32_t));
104 }
105 return arg;
106 }
107#else
108 panic("getArgument() only implemented for FULL_SYSTEM\n");
109 M5_DUMMY_RETURN
110#endif
111}
112
113Fault
114setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2)
115{
116 return new UnimpFault(csprintf("MCR CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n",
117 CRn, opc1, CRm, opc2));
118}
119
120Fault
121readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2)
122{
123 return new UnimpFault(csprintf("MRC CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n",
124 CRn, opc1, CRm, opc2));
125
126}
127
128void
129skipFunction(ThreadContext *tc)
130{
131 TheISA::PCState newPC = tc->pcState();
132 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
133 tc->pcState(newPC);
134}
135
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