1/*
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "arch/arm/utility.hh"
41
42#include <memory>
43
44#include "arch/arm/faults.hh"
45#include "arch/arm/isa_traits.hh"
46#include "arch/arm/system.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/vtophys.hh"
49#include "cpu/base.hh"
50#include "cpu/checker/cpu.hh"
51#include "cpu/thread_context.hh"
52#include "mem/fs_translating_port_proxy.hh"
53#include "sim/full_system.hh"
54
55namespace ArmISA {
56
57void
58initCPU(ThreadContext *tc, int cpuId)
59{
60 // Reset CP15?? What does that mean -- ali
61
62 // FPEXC.EN = 0
63
64 static Fault reset = std::make_shared<Reset>();
65 reset->invoke(tc);
66}
67
68uint64_t
69getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
70{
71 if (!FullSystem) {
72 panic("getArgument() only implemented for full system mode.\n");
73 M5_DUMMY_RETURN
74 }
75
76 if (fp)
77 panic("getArgument(): Floating point arguments not implemented\n");
78
79 if (inAArch64(tc)) {
80 if (size == (uint16_t)(-1))
81 size = sizeof(uint64_t);
82
83 if (number < 8 /*NumArgumentRegs64*/) {
84 return tc->readIntReg(number);
85 } else {
86 panic("getArgument(): No support reading stack args for AArch64\n");
87 }
88 } else {
89 if (size == (uint16_t)(-1))
90 // todo: should this not be sizeof(uint32_t) rather?
91 size = ArmISA::MachineBytes;
92
93 if (number < NumArgumentRegs) {
94 // If the argument is 64 bits, it must be in an even regiser
95 // number. Increment the number here if it isn't even.
96 if (size == sizeof(uint64_t)) {
97 if ((number % 2) != 0)
98 number++;
99 // Read the two halves of the data. Number is inc here to
100 // get the second half of the 64 bit reg.
101 uint64_t tmp;
102 tmp = tc->readIntReg(number++);
103 tmp |= tc->readIntReg(number) << 32;
104 return tmp;
105 } else {
106 return tc->readIntReg(number);
107 }
108 } else {
109 Addr sp = tc->readIntReg(StackPointerReg);
110 FSTranslatingPortProxy &vp = tc->getVirtProxy();
111 uint64_t arg;
112 if (size == sizeof(uint64_t)) {
113 // If the argument is even it must be aligned
114 if ((number % 2) != 0)
115 number++;
116 arg = vp.read<uint64_t>(sp +
117 (number-NumArgumentRegs) * sizeof(uint32_t));
118 // since two 32 bit args == 1 64 bit arg, increment number
119 number++;
120 } else {
121 arg = vp.read<uint32_t>(sp +
122 (number-NumArgumentRegs) * sizeof(uint32_t));
123 }
124 return arg;
125 }
126 }
127 panic("getArgument() should always return\n");
128}
129
130void
131skipFunction(ThreadContext *tc)
132{
133 PCState newPC = tc->pcState();
134 if (inAArch64(tc)) {
135 newPC.set(tc->readIntReg(INTREG_X30));
136 } else {
137 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
138 }
139
140 CheckerCPU *checker = tc->getCheckerCpuPtr();
141 if (checker) {
142 tc->pcStateNoRecord(newPC);
143 } else {
144 tc->pcState(newPC);
145 }
146}
147
148void
149copyRegs(ThreadContext *src, ThreadContext *dest)
150{
151 for (int i = 0; i < NumIntRegs; i++)
152 dest->setIntRegFlat(i, src->readIntRegFlat(i));
153
154 for (int i = 0; i < NumFloatRegs; i++)
155 dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
156
157 for (int i = 0; i < NumVecRegs; i++)
158 dest->setVecRegFlat(i, src->readVecRegFlat(i));
159
160 for (int i = 0; i < NumCCRegs; i++)
161 dest->setCCReg(i, src->readCCReg(i));
162
163 for (int i = 0; i < NumMiscRegs; i++)
164 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
165
166 // setMiscReg "with effect" will set the misc register mapping correctly.
167 // e.g. updateRegMap(val)
168 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
169
170 // Copy over the PC State
171 dest->pcState(src->pcState());
172
173 // Invalidate the tlb misc register cache
174 dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
175 dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
176}
177
178bool
179inSecureState(ThreadContext *tc)
180{
181 SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
182 tc->readMiscReg(MISCREG_SCR);
183 return ArmSystem::haveSecurity(tc) && inSecureState(
184 scr, tc->readMiscReg(MISCREG_CPSR));
185}
186
187inline bool
188isSecureBelowEL3(ThreadContext *tc)
189{
190 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
191 return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
192}
193
194bool
195inAArch64(ThreadContext *tc)
196{
197 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
198 return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
199}
200
201bool
202longDescFormatInUse(ThreadContext *tc)
203{
204 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
205 return ArmSystem::haveLPAE(tc) && ttbcr.eae;
206}
207
208uint32_t
209getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
210{
211 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
212 // Reference Manual
213 //
214 // bit 31 - Multi-processor extensions available
215 // bit 30 - Uni-processor system
216 // bit 24 - Multi-threaded cores
217 // bit 11-8 - Cluster ID
218 // bit 1-0 - CPU ID
219 //
220 // We deliberately extend both the Cluster ID and CPU ID fields to allow
221 // for simulation of larger systems
222 assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
223 assert(tc->socketId() < 65536);
224 if (arm_sys->multiThread) {
225 return 0x80000000 | // multiprocessor extensions available
226 0x01000000 | // multi-threaded cores
227 tc->contextId();
228 } else if (arm_sys->multiProc) {
229 return 0x80000000 | // multiprocessor extensions available
230 tc->cpuId() | tc->socketId() << 8;
231 } else {
232 return 0x80000000 | // multiprocessor extensions available
233 0x40000000 | // in up system
234 tc->cpuId() | tc->socketId() << 8;
235 }
236}
237
238bool
239ELIs64(ThreadContext *tc, ExceptionLevel el)
240{
241 return !ELIs32(tc, el);
242}
243
244bool
245ELIs32(ThreadContext *tc, ExceptionLevel el)
246{
247 bool known, aarch32;
248 std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
249 panic_if(!known, "EL state is UNKNOWN");
250 return aarch32;
251}
252
253std::pair<bool, bool>
254ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
255{
256 // Return true if the specified EL is in aarch32 state.
257 const bool have_el3 = ArmSystem::haveSecurity(tc);
258 const bool have_el2 = ArmSystem::haveVirtualization(tc);
259
260 panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
261 panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
262
263 bool known, aarch32;
264 known = aarch32 = false;
265 if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
266 // Target EL is the highest one in a system where
267 // the highest is using AArch64.
268 known = true; aarch32 = false;
269 } else if (!ArmSystem::highestELIs64(tc)) {
270 // All ELs are using AArch32:
271 known = true; aarch32 = true;
272 } else {
273 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
274 bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
275
276 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
277 bool aarch32_at_el1 = (aarch32_below_el3
278 || (have_el2
279 && !isSecureBelowEL3(tc) && hcr.rw == 0));
280
281 // Only know if EL0 using AArch32 from PSTATE
282 if (el == EL0 && !aarch32_at_el1) {
283 // EL0 controlled by PSTATE
284 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
285
286 known = (cpsr.el == EL0);
287 aarch32 = (cpsr.width == 1);
288 } else {
289 known = true;
290 aarch32 = (aarch32_below_el3 && el != EL3)
291 || (aarch32_at_el1 && (el == EL0 || el == EL1) );
292 }
293 }
294
295 return std::make_pair(known, aarch32);
296}
297
298bool
299isBigEndian64(ThreadContext *tc)
300{
301 switch (opModeToEL(currOpMode(tc))) {
302 case EL3:
303 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
304 case EL2:
305 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
306 case EL1:
307 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
308 case EL0:
309 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
310 default:
311 panic("Invalid exception level");
312 break;
313 }
314}
315
316bool
317badMode32(ThreadContext *tc, OperatingMode mode)
318{
319 return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
320}
321
322bool
323badMode(ThreadContext *tc, OperatingMode mode)
324{
325 return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
326}
327
328Addr
329purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
330 TTBCR tcr)
331{
332 switch (el) {
333 case EL0:
334 case EL1:
335 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
336 return addr | mask(63, 55);
337 else if (!bits(addr, 55, 48) && tcr.tbi0)
338 return bits(addr,55, 0);
339 break;
340 case EL2:
341 assert(ArmSystem::haveVirtualization(tc));
342 tcr = tc->readMiscReg(MISCREG_TCR_EL2);
343 if (tcr.tbi)
344 return addr & mask(56);
345 break;
346 case EL3:
347 assert(ArmSystem::haveSecurity(tc));
348 if (tcr.tbi)
349 return addr & mask(56);
350 break;
351 default:
352 panic("Invalid exception level");
353 break;
354 }
355
356 return addr; // Nothing to do if this is not a tagged address
357}
358
359Addr
360purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
361{
362 TTBCR tcr;
363
364 switch (el) {
365 case EL0:
366 case EL1:
367 tcr = tc->readMiscReg(MISCREG_TCR_EL1);
368 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
369 return addr | mask(63, 55);
370 else if (!bits(addr, 55, 48) && tcr.tbi0)
371 return bits(addr,55, 0);
372 break;
373 case EL2:
374 assert(ArmSystem::haveVirtualization(tc));
375 tcr = tc->readMiscReg(MISCREG_TCR_EL2);
376 if (tcr.tbi)
377 return addr & mask(56);
378 break;
379 case EL3:
380 assert(ArmSystem::haveSecurity(tc));
381 tcr = tc->readMiscReg(MISCREG_TCR_EL3);
382 if (tcr.tbi)
383 return addr & mask(56);
384 break;
385 default:
386 panic("Invalid exception level");
387 break;
388 }
389
390 return addr; // Nothing to do if this is not a tagged address
391}
392
393Addr
394truncPage(Addr addr)
395{
396 return addr & ~(PageBytes - 1);
397}
398
399Addr
400roundPage(Addr addr)
401{
402 return (addr + PageBytes - 1) & ~(PageBytes - 1);
403}
404
405bool
406mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
407 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
408{
409 bool isRead;
410 uint32_t crm;
411 IntRegIndex rt;
412 uint32_t crn;
413 uint32_t opc1;
414 uint32_t opc2;
415 bool trapToHype = false;
416
417
418 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
419 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
420 trapToHype = ((uint32_t) hstr) & (1 << crn);
421 trapToHype |= hdcr.tpm && (crn == 9) && (crm >= 12);
422 trapToHype |= hcr.tidcp && (
423 ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
424 ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
425 ((crn == 11) && ((crm <= 8) || (crm == 15))) );
426
427 if (!trapToHype) {
428 switch (unflattenMiscReg(miscReg)) {
429 case MISCREG_CPACR:
430 trapToHype = hcptr.tcpac;
431 break;
432 case MISCREG_REVIDR:
433 case MISCREG_TCMTR:
434 case MISCREG_TLBTR:
435 case MISCREG_AIDR:
436 trapToHype = hcr.tid1;
437 break;
438 case MISCREG_CTR:
439 case MISCREG_CCSIDR:
440 case MISCREG_CLIDR:
441 case MISCREG_CSSELR:
442 trapToHype = hcr.tid2;
443 break;
444 case MISCREG_ID_PFR0:
445 case MISCREG_ID_PFR1:
446 case MISCREG_ID_DFR0:
447 case MISCREG_ID_AFR0:
448 case MISCREG_ID_MMFR0:
449 case MISCREG_ID_MMFR1:
450 case MISCREG_ID_MMFR2:
451 case MISCREG_ID_MMFR3:
452 case MISCREG_ID_ISAR0:
453 case MISCREG_ID_ISAR1:
454 case MISCREG_ID_ISAR2:
455 case MISCREG_ID_ISAR3:
456 case MISCREG_ID_ISAR4:
457 case MISCREG_ID_ISAR5:
458 trapToHype = hcr.tid3;
459 break;
460 case MISCREG_DCISW:
461 case MISCREG_DCCSW:
462 case MISCREG_DCCISW:
463 trapToHype = hcr.tsw;
464 break;
465 case MISCREG_DCIMVAC:
466 case MISCREG_DCCIMVAC:
467 case MISCREG_DCCMVAC:
468 trapToHype = hcr.tpc;
469 break;
470 case MISCREG_ICIMVAU:
471 case MISCREG_ICIALLU:
472 case MISCREG_ICIALLUIS:
473 case MISCREG_DCCMVAU:
474 trapToHype = hcr.tpu;
475 break;
476 case MISCREG_TLBIALLIS:
477 case MISCREG_TLBIMVAIS:
478 case MISCREG_TLBIASIDIS:
479 case MISCREG_TLBIMVAAIS:
480 case MISCREG_TLBIMVALIS:
481 case MISCREG_TLBIMVAALIS:
482 case MISCREG_DTLBIALL:
483 case MISCREG_ITLBIALL:
484 case MISCREG_DTLBIMVA:
485 case MISCREG_ITLBIMVA:
486 case MISCREG_DTLBIASID:
487 case MISCREG_ITLBIASID:
488 case MISCREG_TLBIMVAA:
489 case MISCREG_TLBIALL:
490 case MISCREG_TLBIMVA:
491 case MISCREG_TLBIMVAL:
492 case MISCREG_TLBIMVAAL:
493 case MISCREG_TLBIASID:
494 trapToHype = hcr.ttlb;
495 break;
496 case MISCREG_ACTLR:
497 trapToHype = hcr.tac;
498 break;
499 case MISCREG_SCTLR:
500 case MISCREG_TTBR0:
501 case MISCREG_TTBR1:
502 case MISCREG_TTBCR:
503 case MISCREG_DACR:
504 case MISCREG_DFSR:
505 case MISCREG_IFSR:
506 case MISCREG_DFAR:
507 case MISCREG_IFAR:
508 case MISCREG_ADFSR:
509 case MISCREG_AIFSR:
510 case MISCREG_PRRR:
511 case MISCREG_NMRR:
512 case MISCREG_MAIR0:
513 case MISCREG_MAIR1:
514 case MISCREG_CONTEXTIDR:
515 trapToHype = hcr.tvm & !isRead;
516 break;
517 case MISCREG_PMCR:
518 trapToHype = hdcr.tpmcr;
519 break;
520 // No default action needed
521 default:
522 break;
523 }
524 }
525 }
526 return trapToHype;
527}
528
529
530bool
531mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
532 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
533{
534 bool isRead;
535 uint32_t crm;
536 IntRegIndex rt;
537 uint32_t crn;
538 uint32_t opc1;
539 uint32_t opc2;
540 bool trapToHype = false;
541
542 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
543 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
544 inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
545 crm, crn, opc1, opc2, hdcr, hcptr, hstr);
546 trapToHype = hdcr.tda && (opc1 == 0);
547 trapToHype |= hcptr.tta && (opc1 == 1);
548 if (!trapToHype) {
549 switch (unflattenMiscReg(miscReg)) {
550 case MISCREG_DBGOSLSR:
551 case MISCREG_DBGOSLAR:
552 case MISCREG_DBGOSDLR:
553 case MISCREG_DBGPRCR:
554 trapToHype = hdcr.tdosa;
555 break;
556 case MISCREG_DBGDRAR:
557 case MISCREG_DBGDSAR:
558 trapToHype = hdcr.tdra;
559 break;
560 case MISCREG_JIDR:
561 trapToHype = hcr.tid0;
562 break;
563 case MISCREG_JOSCR:
564 case MISCREG_JMCR:
565 trapToHype = hstr.tjdbx;
566 break;
567 case MISCREG_TEECR:
568 case MISCREG_TEEHBR:
569 trapToHype = hstr.ttee;
570 break;
571 // No default action needed
572 default:
573 break;
574 }
575 }
576 }
577 return trapToHype;
578}
579
580bool
581mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
582 HCR hcr, uint32_t iss)
583{
584 uint32_t crm;
585 IntRegIndex rt;
586 uint32_t crn;
587 uint32_t opc1;
588 uint32_t opc2;
589 bool isRead;
590 bool trapToHype = false;
591
592 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
593 // This is technically the wrong function, but we can re-use it for
594 // the moment because we only need one field, which overlaps with the
595 // mcrmrc layout
596 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
597 trapToHype = ((uint32_t) hstr) & (1 << crm);
598
599 if (!trapToHype) {
600 switch (unflattenMiscReg(miscReg)) {
601 case MISCREG_SCTLR:
602 case MISCREG_TTBR0:
603 case MISCREG_TTBR1:
604 case MISCREG_TTBCR:
605 case MISCREG_DACR:
606 case MISCREG_DFSR:
607 case MISCREG_IFSR:
608 case MISCREG_DFAR:
609 case MISCREG_IFAR:
610 case MISCREG_ADFSR:
611 case MISCREG_AIFSR:
612 case MISCREG_PRRR:
613 case MISCREG_NMRR:
614 case MISCREG_MAIR0:
615 case MISCREG_MAIR1:
616 case MISCREG_CONTEXTIDR:
617 trapToHype = hcr.tvm & !isRead;
618 break;
619 // No default action needed
620 default:
621 break;
622 }
623 }
624 }
625 return trapToHype;
626}
627
628bool
629msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
630 CPACR cpacr /* CPACR_EL1 */)
631{
632 bool trapToSup = false;
633 switch (miscReg) {
634 case MISCREG_FPCR:
635 case MISCREG_FPSR:
636 case MISCREG_FPEXC32_EL2:
637 if ((el == EL0 && cpacr.fpen != 0x3) ||
638 (el == EL1 && !(cpacr.fpen & 0x1)))
639 trapToSup = true;
640 break;
641 default:
642 break;
643 }
644 return trapToSup;
645}
646
647bool
648msrMrs64TrapToHyp(const MiscRegIndex miscReg,
649 ExceptionLevel el,
650 bool isRead,
651 CPTR cptr /* CPTR_EL2 */,
652 HCR hcr /* HCR_EL2 */,
653 bool * isVfpNeon)
654{
655 bool trapToHyp = false;
656 *isVfpNeon = false;
657
658 switch (miscReg) {
659 // FP/SIMD regs
660 case MISCREG_FPCR:
661 case MISCREG_FPSR:
662 case MISCREG_FPEXC32_EL2:
663 trapToHyp = cptr.tfp;
664 *isVfpNeon = true;
665 break;
666 // CPACR
667 case MISCREG_CPACR_EL1:
668 trapToHyp = cptr.tcpac && el == EL1;
669 break;
670 // Virtual memory control regs
671 case MISCREG_SCTLR_EL1:
672 case MISCREG_TTBR0_EL1:
673 case MISCREG_TTBR1_EL1:
674 case MISCREG_TCR_EL1:
675 case MISCREG_ESR_EL1:
676 case MISCREG_FAR_EL1:
677 case MISCREG_AFSR0_EL1:
678 case MISCREG_AFSR1_EL1:
679 case MISCREG_MAIR_EL1:
680 case MISCREG_AMAIR_EL1:
681 case MISCREG_CONTEXTIDR_EL1:
682 trapToHyp = ((hcr.trvm && isRead) || (hcr.tvm && !isRead))
683 && el == EL1;
684 break;
685 // TLB maintenance instructions
686 case MISCREG_TLBI_VMALLE1:
687 case MISCREG_TLBI_VAE1_Xt:
688 case MISCREG_TLBI_ASIDE1_Xt:
689 case MISCREG_TLBI_VAAE1_Xt:
690 case MISCREG_TLBI_VALE1_Xt:
691 case MISCREG_TLBI_VAALE1_Xt:
692 case MISCREG_TLBI_VMALLE1IS:
693 case MISCREG_TLBI_VAE1IS_Xt:
694 case MISCREG_TLBI_ASIDE1IS_Xt:
695 case MISCREG_TLBI_VAAE1IS_Xt:
696 case MISCREG_TLBI_VALE1IS_Xt:
697 case MISCREG_TLBI_VAALE1IS_Xt:
698 trapToHyp = hcr.ttlb && el == EL1;
699 break;
700 // Cache maintenance instructions to the point of unification
701 case MISCREG_IC_IVAU_Xt:
702 case MISCREG_ICIALLU:
703 case MISCREG_ICIALLUIS:
704 case MISCREG_DC_CVAU_Xt:
705 trapToHyp = hcr.tpu && el <= EL1;
706 break;
707 // Data/Unified cache maintenance instructions to the point of coherency
708 case MISCREG_DC_IVAC_Xt:
709 case MISCREG_DC_CIVAC_Xt:
710 case MISCREG_DC_CVAC_Xt:
711 trapToHyp = hcr.tpc && el <= EL1;
712 break;
713 // Data/Unified cache maintenance instructions by set/way
714 case MISCREG_DC_ISW_Xt:
715 case MISCREG_DC_CSW_Xt:
716 case MISCREG_DC_CISW_Xt:
717 trapToHyp = hcr.tsw && el == EL1;
718 break;
719 // ACTLR
720 case MISCREG_ACTLR_EL1:
721 trapToHyp = hcr.tacr && el == EL1;
722 break;
723
724 // @todo: Trap implementation-dependent functionality based on
725 // hcr.tidcp
726
727 // ID regs, group 3
728 case MISCREG_ID_PFR0_EL1:
729 case MISCREG_ID_PFR1_EL1:
730 case MISCREG_ID_DFR0_EL1:
731 case MISCREG_ID_AFR0_EL1:
732 case MISCREG_ID_MMFR0_EL1:
733 case MISCREG_ID_MMFR1_EL1:
734 case MISCREG_ID_MMFR2_EL1:
735 case MISCREG_ID_MMFR3_EL1:
736 case MISCREG_ID_ISAR0_EL1:
737 case MISCREG_ID_ISAR1_EL1:
738 case MISCREG_ID_ISAR2_EL1:
739 case MISCREG_ID_ISAR3_EL1:
740 case MISCREG_ID_ISAR4_EL1:
741 case MISCREG_ID_ISAR5_EL1:
742 case MISCREG_MVFR0_EL1:
743 case MISCREG_MVFR1_EL1:
744 case MISCREG_MVFR2_EL1:
745 case MISCREG_ID_AA64PFR0_EL1:
746 case MISCREG_ID_AA64PFR1_EL1:
747 case MISCREG_ID_AA64DFR0_EL1:
748 case MISCREG_ID_AA64DFR1_EL1:
749 case MISCREG_ID_AA64ISAR0_EL1:
750 case MISCREG_ID_AA64ISAR1_EL1:
751 case MISCREG_ID_AA64MMFR0_EL1:
752 case MISCREG_ID_AA64MMFR1_EL1:
| 1/*
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#include "arch/arm/utility.hh"
41
42#include <memory>
43
44#include "arch/arm/faults.hh"
45#include "arch/arm/isa_traits.hh"
46#include "arch/arm/system.hh"
47#include "arch/arm/tlb.hh"
48#include "arch/arm/vtophys.hh"
49#include "cpu/base.hh"
50#include "cpu/checker/cpu.hh"
51#include "cpu/thread_context.hh"
52#include "mem/fs_translating_port_proxy.hh"
53#include "sim/full_system.hh"
54
55namespace ArmISA {
56
57void
58initCPU(ThreadContext *tc, int cpuId)
59{
60 // Reset CP15?? What does that mean -- ali
61
62 // FPEXC.EN = 0
63
64 static Fault reset = std::make_shared<Reset>();
65 reset->invoke(tc);
66}
67
68uint64_t
69getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
70{
71 if (!FullSystem) {
72 panic("getArgument() only implemented for full system mode.\n");
73 M5_DUMMY_RETURN
74 }
75
76 if (fp)
77 panic("getArgument(): Floating point arguments not implemented\n");
78
79 if (inAArch64(tc)) {
80 if (size == (uint16_t)(-1))
81 size = sizeof(uint64_t);
82
83 if (number < 8 /*NumArgumentRegs64*/) {
84 return tc->readIntReg(number);
85 } else {
86 panic("getArgument(): No support reading stack args for AArch64\n");
87 }
88 } else {
89 if (size == (uint16_t)(-1))
90 // todo: should this not be sizeof(uint32_t) rather?
91 size = ArmISA::MachineBytes;
92
93 if (number < NumArgumentRegs) {
94 // If the argument is 64 bits, it must be in an even regiser
95 // number. Increment the number here if it isn't even.
96 if (size == sizeof(uint64_t)) {
97 if ((number % 2) != 0)
98 number++;
99 // Read the two halves of the data. Number is inc here to
100 // get the second half of the 64 bit reg.
101 uint64_t tmp;
102 tmp = tc->readIntReg(number++);
103 tmp |= tc->readIntReg(number) << 32;
104 return tmp;
105 } else {
106 return tc->readIntReg(number);
107 }
108 } else {
109 Addr sp = tc->readIntReg(StackPointerReg);
110 FSTranslatingPortProxy &vp = tc->getVirtProxy();
111 uint64_t arg;
112 if (size == sizeof(uint64_t)) {
113 // If the argument is even it must be aligned
114 if ((number % 2) != 0)
115 number++;
116 arg = vp.read<uint64_t>(sp +
117 (number-NumArgumentRegs) * sizeof(uint32_t));
118 // since two 32 bit args == 1 64 bit arg, increment number
119 number++;
120 } else {
121 arg = vp.read<uint32_t>(sp +
122 (number-NumArgumentRegs) * sizeof(uint32_t));
123 }
124 return arg;
125 }
126 }
127 panic("getArgument() should always return\n");
128}
129
130void
131skipFunction(ThreadContext *tc)
132{
133 PCState newPC = tc->pcState();
134 if (inAArch64(tc)) {
135 newPC.set(tc->readIntReg(INTREG_X30));
136 } else {
137 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
138 }
139
140 CheckerCPU *checker = tc->getCheckerCpuPtr();
141 if (checker) {
142 tc->pcStateNoRecord(newPC);
143 } else {
144 tc->pcState(newPC);
145 }
146}
147
148void
149copyRegs(ThreadContext *src, ThreadContext *dest)
150{
151 for (int i = 0; i < NumIntRegs; i++)
152 dest->setIntRegFlat(i, src->readIntRegFlat(i));
153
154 for (int i = 0; i < NumFloatRegs; i++)
155 dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
156
157 for (int i = 0; i < NumVecRegs; i++)
158 dest->setVecRegFlat(i, src->readVecRegFlat(i));
159
160 for (int i = 0; i < NumCCRegs; i++)
161 dest->setCCReg(i, src->readCCReg(i));
162
163 for (int i = 0; i < NumMiscRegs; i++)
164 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
165
166 // setMiscReg "with effect" will set the misc register mapping correctly.
167 // e.g. updateRegMap(val)
168 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
169
170 // Copy over the PC State
171 dest->pcState(src->pcState());
172
173 // Invalidate the tlb misc register cache
174 dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
175 dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
176}
177
178bool
179inSecureState(ThreadContext *tc)
180{
181 SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
182 tc->readMiscReg(MISCREG_SCR);
183 return ArmSystem::haveSecurity(tc) && inSecureState(
184 scr, tc->readMiscReg(MISCREG_CPSR));
185}
186
187inline bool
188isSecureBelowEL3(ThreadContext *tc)
189{
190 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
191 return ArmSystem::haveEL(tc, EL3) && scr.ns == 0;
192}
193
194bool
195inAArch64(ThreadContext *tc)
196{
197 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
198 return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
199}
200
201bool
202longDescFormatInUse(ThreadContext *tc)
203{
204 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
205 return ArmSystem::haveLPAE(tc) && ttbcr.eae;
206}
207
208uint32_t
209getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
210{
211 // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
212 // Reference Manual
213 //
214 // bit 31 - Multi-processor extensions available
215 // bit 30 - Uni-processor system
216 // bit 24 - Multi-threaded cores
217 // bit 11-8 - Cluster ID
218 // bit 1-0 - CPU ID
219 //
220 // We deliberately extend both the Cluster ID and CPU ID fields to allow
221 // for simulation of larger systems
222 assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
223 assert(tc->socketId() < 65536);
224 if (arm_sys->multiThread) {
225 return 0x80000000 | // multiprocessor extensions available
226 0x01000000 | // multi-threaded cores
227 tc->contextId();
228 } else if (arm_sys->multiProc) {
229 return 0x80000000 | // multiprocessor extensions available
230 tc->cpuId() | tc->socketId() << 8;
231 } else {
232 return 0x80000000 | // multiprocessor extensions available
233 0x40000000 | // in up system
234 tc->cpuId() | tc->socketId() << 8;
235 }
236}
237
238bool
239ELIs64(ThreadContext *tc, ExceptionLevel el)
240{
241 return !ELIs32(tc, el);
242}
243
244bool
245ELIs32(ThreadContext *tc, ExceptionLevel el)
246{
247 bool known, aarch32;
248 std::tie(known, aarch32) = ELUsingAArch32K(tc, el);
249 panic_if(!known, "EL state is UNKNOWN");
250 return aarch32;
251}
252
253std::pair<bool, bool>
254ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
255{
256 // Return true if the specified EL is in aarch32 state.
257 const bool have_el3 = ArmSystem::haveSecurity(tc);
258 const bool have_el2 = ArmSystem::haveVirtualization(tc);
259
260 panic_if(el == EL2 && !have_el2, "Asking for EL2 when it doesn't exist");
261 panic_if(el == EL3 && !have_el3, "Asking for EL3 when it doesn't exist");
262
263 bool known, aarch32;
264 known = aarch32 = false;
265 if (ArmSystem::highestELIs64(tc) && ArmSystem::highestEL(tc) == el) {
266 // Target EL is the highest one in a system where
267 // the highest is using AArch64.
268 known = true; aarch32 = false;
269 } else if (!ArmSystem::highestELIs64(tc)) {
270 // All ELs are using AArch32:
271 known = true; aarch32 = true;
272 } else {
273 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
274 bool aarch32_below_el3 = (have_el3 && scr.rw == 0);
275
276 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
277 bool aarch32_at_el1 = (aarch32_below_el3
278 || (have_el2
279 && !isSecureBelowEL3(tc) && hcr.rw == 0));
280
281 // Only know if EL0 using AArch32 from PSTATE
282 if (el == EL0 && !aarch32_at_el1) {
283 // EL0 controlled by PSTATE
284 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
285
286 known = (cpsr.el == EL0);
287 aarch32 = (cpsr.width == 1);
288 } else {
289 known = true;
290 aarch32 = (aarch32_below_el3 && el != EL3)
291 || (aarch32_at_el1 && (el == EL0 || el == EL1) );
292 }
293 }
294
295 return std::make_pair(known, aarch32);
296}
297
298bool
299isBigEndian64(ThreadContext *tc)
300{
301 switch (opModeToEL(currOpMode(tc))) {
302 case EL3:
303 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
304 case EL2:
305 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
306 case EL1:
307 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
308 case EL0:
309 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
310 default:
311 panic("Invalid exception level");
312 break;
313 }
314}
315
316bool
317badMode32(ThreadContext *tc, OperatingMode mode)
318{
319 return unknownMode32(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
320}
321
322bool
323badMode(ThreadContext *tc, OperatingMode mode)
324{
325 return unknownMode(mode) || !ArmSystem::haveEL(tc, opModeToEL(mode));
326}
327
328Addr
329purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
330 TTBCR tcr)
331{
332 switch (el) {
333 case EL0:
334 case EL1:
335 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
336 return addr | mask(63, 55);
337 else if (!bits(addr, 55, 48) && tcr.tbi0)
338 return bits(addr,55, 0);
339 break;
340 case EL2:
341 assert(ArmSystem::haveVirtualization(tc));
342 tcr = tc->readMiscReg(MISCREG_TCR_EL2);
343 if (tcr.tbi)
344 return addr & mask(56);
345 break;
346 case EL3:
347 assert(ArmSystem::haveSecurity(tc));
348 if (tcr.tbi)
349 return addr & mask(56);
350 break;
351 default:
352 panic("Invalid exception level");
353 break;
354 }
355
356 return addr; // Nothing to do if this is not a tagged address
357}
358
359Addr
360purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
361{
362 TTBCR tcr;
363
364 switch (el) {
365 case EL0:
366 case EL1:
367 tcr = tc->readMiscReg(MISCREG_TCR_EL1);
368 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1)
369 return addr | mask(63, 55);
370 else if (!bits(addr, 55, 48) && tcr.tbi0)
371 return bits(addr,55, 0);
372 break;
373 case EL2:
374 assert(ArmSystem::haveVirtualization(tc));
375 tcr = tc->readMiscReg(MISCREG_TCR_EL2);
376 if (tcr.tbi)
377 return addr & mask(56);
378 break;
379 case EL3:
380 assert(ArmSystem::haveSecurity(tc));
381 tcr = tc->readMiscReg(MISCREG_TCR_EL3);
382 if (tcr.tbi)
383 return addr & mask(56);
384 break;
385 default:
386 panic("Invalid exception level");
387 break;
388 }
389
390 return addr; // Nothing to do if this is not a tagged address
391}
392
393Addr
394truncPage(Addr addr)
395{
396 return addr & ~(PageBytes - 1);
397}
398
399Addr
400roundPage(Addr addr)
401{
402 return (addr + PageBytes - 1) & ~(PageBytes - 1);
403}
404
405bool
406mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
407 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
408{
409 bool isRead;
410 uint32_t crm;
411 IntRegIndex rt;
412 uint32_t crn;
413 uint32_t opc1;
414 uint32_t opc2;
415 bool trapToHype = false;
416
417
418 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
419 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
420 trapToHype = ((uint32_t) hstr) & (1 << crn);
421 trapToHype |= hdcr.tpm && (crn == 9) && (crm >= 12);
422 trapToHype |= hcr.tidcp && (
423 ((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
424 ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
425 ((crn == 11) && ((crm <= 8) || (crm == 15))) );
426
427 if (!trapToHype) {
428 switch (unflattenMiscReg(miscReg)) {
429 case MISCREG_CPACR:
430 trapToHype = hcptr.tcpac;
431 break;
432 case MISCREG_REVIDR:
433 case MISCREG_TCMTR:
434 case MISCREG_TLBTR:
435 case MISCREG_AIDR:
436 trapToHype = hcr.tid1;
437 break;
438 case MISCREG_CTR:
439 case MISCREG_CCSIDR:
440 case MISCREG_CLIDR:
441 case MISCREG_CSSELR:
442 trapToHype = hcr.tid2;
443 break;
444 case MISCREG_ID_PFR0:
445 case MISCREG_ID_PFR1:
446 case MISCREG_ID_DFR0:
447 case MISCREG_ID_AFR0:
448 case MISCREG_ID_MMFR0:
449 case MISCREG_ID_MMFR1:
450 case MISCREG_ID_MMFR2:
451 case MISCREG_ID_MMFR3:
452 case MISCREG_ID_ISAR0:
453 case MISCREG_ID_ISAR1:
454 case MISCREG_ID_ISAR2:
455 case MISCREG_ID_ISAR3:
456 case MISCREG_ID_ISAR4:
457 case MISCREG_ID_ISAR5:
458 trapToHype = hcr.tid3;
459 break;
460 case MISCREG_DCISW:
461 case MISCREG_DCCSW:
462 case MISCREG_DCCISW:
463 trapToHype = hcr.tsw;
464 break;
465 case MISCREG_DCIMVAC:
466 case MISCREG_DCCIMVAC:
467 case MISCREG_DCCMVAC:
468 trapToHype = hcr.tpc;
469 break;
470 case MISCREG_ICIMVAU:
471 case MISCREG_ICIALLU:
472 case MISCREG_ICIALLUIS:
473 case MISCREG_DCCMVAU:
474 trapToHype = hcr.tpu;
475 break;
476 case MISCREG_TLBIALLIS:
477 case MISCREG_TLBIMVAIS:
478 case MISCREG_TLBIASIDIS:
479 case MISCREG_TLBIMVAAIS:
480 case MISCREG_TLBIMVALIS:
481 case MISCREG_TLBIMVAALIS:
482 case MISCREG_DTLBIALL:
483 case MISCREG_ITLBIALL:
484 case MISCREG_DTLBIMVA:
485 case MISCREG_ITLBIMVA:
486 case MISCREG_DTLBIASID:
487 case MISCREG_ITLBIASID:
488 case MISCREG_TLBIMVAA:
489 case MISCREG_TLBIALL:
490 case MISCREG_TLBIMVA:
491 case MISCREG_TLBIMVAL:
492 case MISCREG_TLBIMVAAL:
493 case MISCREG_TLBIASID:
494 trapToHype = hcr.ttlb;
495 break;
496 case MISCREG_ACTLR:
497 trapToHype = hcr.tac;
498 break;
499 case MISCREG_SCTLR:
500 case MISCREG_TTBR0:
501 case MISCREG_TTBR1:
502 case MISCREG_TTBCR:
503 case MISCREG_DACR:
504 case MISCREG_DFSR:
505 case MISCREG_IFSR:
506 case MISCREG_DFAR:
507 case MISCREG_IFAR:
508 case MISCREG_ADFSR:
509 case MISCREG_AIFSR:
510 case MISCREG_PRRR:
511 case MISCREG_NMRR:
512 case MISCREG_MAIR0:
513 case MISCREG_MAIR1:
514 case MISCREG_CONTEXTIDR:
515 trapToHype = hcr.tvm & !isRead;
516 break;
517 case MISCREG_PMCR:
518 trapToHype = hdcr.tpmcr;
519 break;
520 // No default action needed
521 default:
522 break;
523 }
524 }
525 }
526 return trapToHype;
527}
528
529
530bool
531mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
532 HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
533{
534 bool isRead;
535 uint32_t crm;
536 IntRegIndex rt;
537 uint32_t crn;
538 uint32_t opc1;
539 uint32_t opc2;
540 bool trapToHype = false;
541
542 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
543 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
544 inform("trap check M:%x N:%x 1:%x 2:%x hdcr %x, hcptr %x, hstr %x\n",
545 crm, crn, opc1, opc2, hdcr, hcptr, hstr);
546 trapToHype = hdcr.tda && (opc1 == 0);
547 trapToHype |= hcptr.tta && (opc1 == 1);
548 if (!trapToHype) {
549 switch (unflattenMiscReg(miscReg)) {
550 case MISCREG_DBGOSLSR:
551 case MISCREG_DBGOSLAR:
552 case MISCREG_DBGOSDLR:
553 case MISCREG_DBGPRCR:
554 trapToHype = hdcr.tdosa;
555 break;
556 case MISCREG_DBGDRAR:
557 case MISCREG_DBGDSAR:
558 trapToHype = hdcr.tdra;
559 break;
560 case MISCREG_JIDR:
561 trapToHype = hcr.tid0;
562 break;
563 case MISCREG_JOSCR:
564 case MISCREG_JMCR:
565 trapToHype = hstr.tjdbx;
566 break;
567 case MISCREG_TEECR:
568 case MISCREG_TEEHBR:
569 trapToHype = hstr.ttee;
570 break;
571 // No default action needed
572 default:
573 break;
574 }
575 }
576 }
577 return trapToHype;
578}
579
580bool
581mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
582 HCR hcr, uint32_t iss)
583{
584 uint32_t crm;
585 IntRegIndex rt;
586 uint32_t crn;
587 uint32_t opc1;
588 uint32_t opc2;
589 bool isRead;
590 bool trapToHype = false;
591
592 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
593 // This is technically the wrong function, but we can re-use it for
594 // the moment because we only need one field, which overlaps with the
595 // mcrmrc layout
596 mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
597 trapToHype = ((uint32_t) hstr) & (1 << crm);
598
599 if (!trapToHype) {
600 switch (unflattenMiscReg(miscReg)) {
601 case MISCREG_SCTLR:
602 case MISCREG_TTBR0:
603 case MISCREG_TTBR1:
604 case MISCREG_TTBCR:
605 case MISCREG_DACR:
606 case MISCREG_DFSR:
607 case MISCREG_IFSR:
608 case MISCREG_DFAR:
609 case MISCREG_IFAR:
610 case MISCREG_ADFSR:
611 case MISCREG_AIFSR:
612 case MISCREG_PRRR:
613 case MISCREG_NMRR:
614 case MISCREG_MAIR0:
615 case MISCREG_MAIR1:
616 case MISCREG_CONTEXTIDR:
617 trapToHype = hcr.tvm & !isRead;
618 break;
619 // No default action needed
620 default:
621 break;
622 }
623 }
624 }
625 return trapToHype;
626}
627
628bool
629msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
630 CPACR cpacr /* CPACR_EL1 */)
631{
632 bool trapToSup = false;
633 switch (miscReg) {
634 case MISCREG_FPCR:
635 case MISCREG_FPSR:
636 case MISCREG_FPEXC32_EL2:
637 if ((el == EL0 && cpacr.fpen != 0x3) ||
638 (el == EL1 && !(cpacr.fpen & 0x1)))
639 trapToSup = true;
640 break;
641 default:
642 break;
643 }
644 return trapToSup;
645}
646
647bool
648msrMrs64TrapToHyp(const MiscRegIndex miscReg,
649 ExceptionLevel el,
650 bool isRead,
651 CPTR cptr /* CPTR_EL2 */,
652 HCR hcr /* HCR_EL2 */,
653 bool * isVfpNeon)
654{
655 bool trapToHyp = false;
656 *isVfpNeon = false;
657
658 switch (miscReg) {
659 // FP/SIMD regs
660 case MISCREG_FPCR:
661 case MISCREG_FPSR:
662 case MISCREG_FPEXC32_EL2:
663 trapToHyp = cptr.tfp;
664 *isVfpNeon = true;
665 break;
666 // CPACR
667 case MISCREG_CPACR_EL1:
668 trapToHyp = cptr.tcpac && el == EL1;
669 break;
670 // Virtual memory control regs
671 case MISCREG_SCTLR_EL1:
672 case MISCREG_TTBR0_EL1:
673 case MISCREG_TTBR1_EL1:
674 case MISCREG_TCR_EL1:
675 case MISCREG_ESR_EL1:
676 case MISCREG_FAR_EL1:
677 case MISCREG_AFSR0_EL1:
678 case MISCREG_AFSR1_EL1:
679 case MISCREG_MAIR_EL1:
680 case MISCREG_AMAIR_EL1:
681 case MISCREG_CONTEXTIDR_EL1:
682 trapToHyp = ((hcr.trvm && isRead) || (hcr.tvm && !isRead))
683 && el == EL1;
684 break;
685 // TLB maintenance instructions
686 case MISCREG_TLBI_VMALLE1:
687 case MISCREG_TLBI_VAE1_Xt:
688 case MISCREG_TLBI_ASIDE1_Xt:
689 case MISCREG_TLBI_VAAE1_Xt:
690 case MISCREG_TLBI_VALE1_Xt:
691 case MISCREG_TLBI_VAALE1_Xt:
692 case MISCREG_TLBI_VMALLE1IS:
693 case MISCREG_TLBI_VAE1IS_Xt:
694 case MISCREG_TLBI_ASIDE1IS_Xt:
695 case MISCREG_TLBI_VAAE1IS_Xt:
696 case MISCREG_TLBI_VALE1IS_Xt:
697 case MISCREG_TLBI_VAALE1IS_Xt:
698 trapToHyp = hcr.ttlb && el == EL1;
699 break;
700 // Cache maintenance instructions to the point of unification
701 case MISCREG_IC_IVAU_Xt:
702 case MISCREG_ICIALLU:
703 case MISCREG_ICIALLUIS:
704 case MISCREG_DC_CVAU_Xt:
705 trapToHyp = hcr.tpu && el <= EL1;
706 break;
707 // Data/Unified cache maintenance instructions to the point of coherency
708 case MISCREG_DC_IVAC_Xt:
709 case MISCREG_DC_CIVAC_Xt:
710 case MISCREG_DC_CVAC_Xt:
711 trapToHyp = hcr.tpc && el <= EL1;
712 break;
713 // Data/Unified cache maintenance instructions by set/way
714 case MISCREG_DC_ISW_Xt:
715 case MISCREG_DC_CSW_Xt:
716 case MISCREG_DC_CISW_Xt:
717 trapToHyp = hcr.tsw && el == EL1;
718 break;
719 // ACTLR
720 case MISCREG_ACTLR_EL1:
721 trapToHyp = hcr.tacr && el == EL1;
722 break;
723
724 // @todo: Trap implementation-dependent functionality based on
725 // hcr.tidcp
726
727 // ID regs, group 3
728 case MISCREG_ID_PFR0_EL1:
729 case MISCREG_ID_PFR1_EL1:
730 case MISCREG_ID_DFR0_EL1:
731 case MISCREG_ID_AFR0_EL1:
732 case MISCREG_ID_MMFR0_EL1:
733 case MISCREG_ID_MMFR1_EL1:
734 case MISCREG_ID_MMFR2_EL1:
735 case MISCREG_ID_MMFR3_EL1:
736 case MISCREG_ID_ISAR0_EL1:
737 case MISCREG_ID_ISAR1_EL1:
738 case MISCREG_ID_ISAR2_EL1:
739 case MISCREG_ID_ISAR3_EL1:
740 case MISCREG_ID_ISAR4_EL1:
741 case MISCREG_ID_ISAR5_EL1:
742 case MISCREG_MVFR0_EL1:
743 case MISCREG_MVFR1_EL1:
744 case MISCREG_MVFR2_EL1:
745 case MISCREG_ID_AA64PFR0_EL1:
746 case MISCREG_ID_AA64PFR1_EL1:
747 case MISCREG_ID_AA64DFR0_EL1:
748 case MISCREG_ID_AA64DFR1_EL1:
749 case MISCREG_ID_AA64ISAR0_EL1:
750 case MISCREG_ID_AA64ISAR1_EL1:
751 case MISCREG_ID_AA64MMFR0_EL1:
752 case MISCREG_ID_AA64MMFR1_EL1:
|
753 case MISCREG_ID_AA64AFR0_EL1:
754 case MISCREG_ID_AA64AFR1_EL1:
755 assert(isRead);
756 trapToHyp = hcr.tid3 && el == EL1;
757 break;
758 // ID regs, group 2
759 case MISCREG_CTR_EL0:
760 case MISCREG_CCSIDR_EL1:
761 case MISCREG_CLIDR_EL1:
762 case MISCREG_CSSELR_EL1:
763 trapToHyp = hcr.tid2 && el <= EL1;
764 break;
765 // ID regs, group 1
766 case MISCREG_AIDR_EL1:
767 case MISCREG_REVIDR_EL1:
768 assert(isRead);
769 trapToHyp = hcr.tid1 && el == EL1;
770 break;
771 default:
772 break;
773 }
774 return trapToHyp;
775}
776
777bool
778msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr /* CPTR_EL3 */,
779 ExceptionLevel el, bool * isVfpNeon)
780{
781 bool trapToMon = false;
782 *isVfpNeon = false;
783
784 switch (miscReg) {
785 // FP/SIMD regs
786 case MISCREG_FPCR:
787 case MISCREG_FPSR:
788 case MISCREG_FPEXC32_EL2:
789 trapToMon = cptr.tfp;
790 *isVfpNeon = true;
791 break;
792 // CPACR, CPTR
793 case MISCREG_CPACR_EL1:
794 if (el == EL1) {
795 trapToMon = cptr.tcpac;
796 }
797 break;
798 case MISCREG_CPTR_EL2:
799 if (el == EL2) {
800 trapToMon = cptr.tcpac;
801 }
802 break;
803 default:
804 break;
805 }
806 return trapToMon;
807}
808
809bool
810decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
811 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
812{
813 OperatingMode mode = MODE_UNDEFINED;
814 bool ok = true;
815
816 // R mostly indicates if its a int register or a misc reg, we override
817 // below if the few corner cases
818 isIntReg = !r;
819 // Loosely based on ARM ARM issue C section B9.3.10
820 if (r) {
821 switch (sysM)
822 {
823 case 0xE:
824 regIdx = MISCREG_SPSR_FIQ;
825 mode = MODE_FIQ;
826 break;
827 case 0x10:
828 regIdx = MISCREG_SPSR_IRQ;
829 mode = MODE_IRQ;
830 break;
831 case 0x12:
832 regIdx = MISCREG_SPSR_SVC;
833 mode = MODE_SVC;
834 break;
835 case 0x14:
836 regIdx = MISCREG_SPSR_ABT;
837 mode = MODE_ABORT;
838 break;
839 case 0x16:
840 regIdx = MISCREG_SPSR_UND;
841 mode = MODE_UNDEFINED;
842 break;
843 case 0x1C:
844 regIdx = MISCREG_SPSR_MON;
845 mode = MODE_MON;
846 break;
847 case 0x1E:
848 regIdx = MISCREG_SPSR_HYP;
849 mode = MODE_HYP;
850 break;
851 default:
852 ok = false;
853 break;
854 }
855 } else {
856 int sysM4To3 = bits(sysM, 4, 3);
857
858 if (sysM4To3 == 0) {
859 mode = MODE_USER;
860 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
861 } else if (sysM4To3 == 1) {
862 mode = MODE_FIQ;
863 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
864 } else if (sysM4To3 == 3) {
865 if (bits(sysM, 1) == 0) {
866 mode = MODE_MON;
867 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
868 } else {
869 mode = MODE_HYP;
870 if (bits(sysM, 0) == 1) {
871 regIdx = intRegInMode(mode, 13); // R13 in HYP
872 } else {
873 isIntReg = false;
874 regIdx = MISCREG_ELR_HYP;
875 }
876 }
877 } else { // Other Banked registers
878 int sysM2 = bits(sysM, 2);
879 int sysM1 = bits(sysM, 1);
880
881 mode = (OperatingMode) ( ((sysM2 || sysM1) << 0) |
882 (1 << 1) |
883 ((sysM2 && !sysM1) << 2) |
884 ((sysM2 && sysM1) << 3) |
885 (1 << 4) );
886 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
887 // Don't flatten the register here. This is going to go through
888 // setIntReg() which will do the flattening
889 ok &= mode != cpsr.mode;
890 }
891 }
892
893 // Check that the requested register is accessable from the current mode
894 if (ok && checkSecurity && mode != cpsr.mode) {
895 switch (cpsr.mode)
896 {
897 case MODE_USER:
898 ok = false;
899 break;
900 case MODE_FIQ:
901 ok &= mode != MODE_HYP;
902 ok &= (mode != MODE_MON) || !scr.ns;
903 break;
904 case MODE_HYP:
905 ok &= mode != MODE_MON;
906 ok &= (mode != MODE_FIQ) || !nsacr.rfr;
907 break;
908 case MODE_IRQ:
909 case MODE_SVC:
910 case MODE_ABORT:
911 case MODE_UNDEFINED:
912 case MODE_SYSTEM:
913 ok &= mode != MODE_HYP;
914 ok &= (mode != MODE_MON) || !scr.ns;
915 ok &= (mode != MODE_FIQ) || !nsacr.rfr;
916 break;
917 // can access everything, no further checks required
918 case MODE_MON:
919 break;
920 default:
921 panic("unknown Mode 0x%x\n", cpsr.mode);
922 break;
923 }
924 }
925 return (ok);
926}
927
928bool
929SPAlignmentCheckEnabled(ThreadContext* tc)
930{
931 switch (opModeToEL(currOpMode(tc))) {
932 case EL3:
933 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
934 case EL2:
935 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
936 case EL1:
937 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
938 case EL0:
939 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
940 default:
941 panic("Invalid exception level");
942 break;
943 }
944}
945
946int
947decodePhysAddrRange64(uint8_t pa_enc)
948{
949 switch (pa_enc) {
950 case 0x0:
951 return 32;
952 case 0x1:
953 return 36;
954 case 0x2:
955 return 40;
956 case 0x3:
957 return 42;
958 case 0x4:
959 return 44;
960 case 0x5:
961 case 0x6:
962 case 0x7:
963 return 48;
964 default:
965 panic("Invalid phys. address range encoding");
966 }
967}
968
969uint8_t
970encodePhysAddrRange64(int pa_size)
971{
972 switch (pa_size) {
973 case 32:
974 return 0x0;
975 case 36:
976 return 0x1;
977 case 40:
978 return 0x2;
979 case 42:
980 return 0x3;
981 case 44:
982 return 0x4;
983 case 48:
984 return 0x5;
985 default:
986 panic("Invalid phys. address range");
987 }
988}
989
990} // namespace ArmISA
| 754 case MISCREG_ID_AA64AFR0_EL1:
755 case MISCREG_ID_AA64AFR1_EL1:
756 assert(isRead);
757 trapToHyp = hcr.tid3 && el == EL1;
758 break;
759 // ID regs, group 2
760 case MISCREG_CTR_EL0:
761 case MISCREG_CCSIDR_EL1:
762 case MISCREG_CLIDR_EL1:
763 case MISCREG_CSSELR_EL1:
764 trapToHyp = hcr.tid2 && el <= EL1;
765 break;
766 // ID regs, group 1
767 case MISCREG_AIDR_EL1:
768 case MISCREG_REVIDR_EL1:
769 assert(isRead);
770 trapToHyp = hcr.tid1 && el == EL1;
771 break;
772 default:
773 break;
774 }
775 return trapToHyp;
776}
777
778bool
779msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr /* CPTR_EL3 */,
780 ExceptionLevel el, bool * isVfpNeon)
781{
782 bool trapToMon = false;
783 *isVfpNeon = false;
784
785 switch (miscReg) {
786 // FP/SIMD regs
787 case MISCREG_FPCR:
788 case MISCREG_FPSR:
789 case MISCREG_FPEXC32_EL2:
790 trapToMon = cptr.tfp;
791 *isVfpNeon = true;
792 break;
793 // CPACR, CPTR
794 case MISCREG_CPACR_EL1:
795 if (el == EL1) {
796 trapToMon = cptr.tcpac;
797 }
798 break;
799 case MISCREG_CPTR_EL2:
800 if (el == EL2) {
801 trapToMon = cptr.tcpac;
802 }
803 break;
804 default:
805 break;
806 }
807 return trapToMon;
808}
809
810bool
811decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
812 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
813{
814 OperatingMode mode = MODE_UNDEFINED;
815 bool ok = true;
816
817 // R mostly indicates if its a int register or a misc reg, we override
818 // below if the few corner cases
819 isIntReg = !r;
820 // Loosely based on ARM ARM issue C section B9.3.10
821 if (r) {
822 switch (sysM)
823 {
824 case 0xE:
825 regIdx = MISCREG_SPSR_FIQ;
826 mode = MODE_FIQ;
827 break;
828 case 0x10:
829 regIdx = MISCREG_SPSR_IRQ;
830 mode = MODE_IRQ;
831 break;
832 case 0x12:
833 regIdx = MISCREG_SPSR_SVC;
834 mode = MODE_SVC;
835 break;
836 case 0x14:
837 regIdx = MISCREG_SPSR_ABT;
838 mode = MODE_ABORT;
839 break;
840 case 0x16:
841 regIdx = MISCREG_SPSR_UND;
842 mode = MODE_UNDEFINED;
843 break;
844 case 0x1C:
845 regIdx = MISCREG_SPSR_MON;
846 mode = MODE_MON;
847 break;
848 case 0x1E:
849 regIdx = MISCREG_SPSR_HYP;
850 mode = MODE_HYP;
851 break;
852 default:
853 ok = false;
854 break;
855 }
856 } else {
857 int sysM4To3 = bits(sysM, 4, 3);
858
859 if (sysM4To3 == 0) {
860 mode = MODE_USER;
861 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
862 } else if (sysM4To3 == 1) {
863 mode = MODE_FIQ;
864 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
865 } else if (sysM4To3 == 3) {
866 if (bits(sysM, 1) == 0) {
867 mode = MODE_MON;
868 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
869 } else {
870 mode = MODE_HYP;
871 if (bits(sysM, 0) == 1) {
872 regIdx = intRegInMode(mode, 13); // R13 in HYP
873 } else {
874 isIntReg = false;
875 regIdx = MISCREG_ELR_HYP;
876 }
877 }
878 } else { // Other Banked registers
879 int sysM2 = bits(sysM, 2);
880 int sysM1 = bits(sysM, 1);
881
882 mode = (OperatingMode) ( ((sysM2 || sysM1) << 0) |
883 (1 << 1) |
884 ((sysM2 && !sysM1) << 2) |
885 ((sysM2 && sysM1) << 3) |
886 (1 << 4) );
887 regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
888 // Don't flatten the register here. This is going to go through
889 // setIntReg() which will do the flattening
890 ok &= mode != cpsr.mode;
891 }
892 }
893
894 // Check that the requested register is accessable from the current mode
895 if (ok && checkSecurity && mode != cpsr.mode) {
896 switch (cpsr.mode)
897 {
898 case MODE_USER:
899 ok = false;
900 break;
901 case MODE_FIQ:
902 ok &= mode != MODE_HYP;
903 ok &= (mode != MODE_MON) || !scr.ns;
904 break;
905 case MODE_HYP:
906 ok &= mode != MODE_MON;
907 ok &= (mode != MODE_FIQ) || !nsacr.rfr;
908 break;
909 case MODE_IRQ:
910 case MODE_SVC:
911 case MODE_ABORT:
912 case MODE_UNDEFINED:
913 case MODE_SYSTEM:
914 ok &= mode != MODE_HYP;
915 ok &= (mode != MODE_MON) || !scr.ns;
916 ok &= (mode != MODE_FIQ) || !nsacr.rfr;
917 break;
918 // can access everything, no further checks required
919 case MODE_MON:
920 break;
921 default:
922 panic("unknown Mode 0x%x\n", cpsr.mode);
923 break;
924 }
925 }
926 return (ok);
927}
928
929bool
930SPAlignmentCheckEnabled(ThreadContext* tc)
931{
932 switch (opModeToEL(currOpMode(tc))) {
933 case EL3:
934 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
935 case EL2:
936 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
937 case EL1:
938 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
939 case EL0:
940 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
941 default:
942 panic("Invalid exception level");
943 break;
944 }
945}
946
947int
948decodePhysAddrRange64(uint8_t pa_enc)
949{
950 switch (pa_enc) {
951 case 0x0:
952 return 32;
953 case 0x1:
954 return 36;
955 case 0x2:
956 return 40;
957 case 0x3:
958 return 42;
959 case 0x4:
960 return 44;
961 case 0x5:
962 case 0x6:
963 case 0x7:
964 return 48;
965 default:
966 panic("Invalid phys. address range encoding");
967 }
968}
969
970uint8_t
971encodePhysAddrRange64(int pa_size)
972{
973 switch (pa_size) {
974 case 32:
975 return 0x0;
976 case 36:
977 return 0x1;
978 case 40:
979 return 0x2;
980 case 42:
981 return 0x3;
982 case 44:
983 return 0x4;
984 case 48:
985 return 0x5;
986 default:
987 panic("Invalid phys. address range");
988 }
989}
990
991} // namespace ArmISA
|