1/*
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
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621 break;
622 }
623 }
624 }
625 return trapToHype;
626}
627
628bool
629decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
630 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
631{
632 OperatingMode mode = MODE_UNDEFINED;
633 bool ok = true;
634
635 // R mostly indicates if its a int register or a misc reg, we override
636 // below if the few corner cases
--- 173 unchanged lines hidden ---
2 * Copyright (c) 2009-2014, 2016-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
--- 612 unchanged lines hidden (view full) ---
621 break;
622 }
623 }
624 }
625 return trapToHype;
626}
627
628bool
629decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
630 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
631{
632 OperatingMode mode = MODE_UNDEFINED;
633 bool ok = true;
634
635 // R mostly indicates if its a int register or a misc reg, we override
636 // below if the few corner cases
--- 173 unchanged lines hidden ---