types.hh (9074:f58f93f1656c) types.hh (10037:5cac77888310)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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77
78 // FPSCR fields
79 Bitfield<41, 40> fpscrStride;
80 Bitfield<39, 37> fpscrLen;
81
82 // Bitfields to select mode.
83 Bitfield<36> thumb;
84 Bitfield<35> bigThumb;
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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77
78 // FPSCR fields
79 Bitfield<41, 40> fpscrStride;
80 Bitfield<39, 37> fpscrLen;
81
82 // Bitfields to select mode.
83 Bitfield<36> thumb;
84 Bitfield<35> bigThumb;
85 Bitfield<34> aarch64;
85
86 // Made up bitfields that make life easier.
87 Bitfield<33> sevenAndFour;
88 Bitfield<32> isMisc;
89
90 uint32_t instBits;
91
92 // All the different types of opcode fields.

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138
139 Bitfield<11, 0> immed11_0;
140 Bitfield<7, 0> immed7_0;
141
142 Bitfield<11, 8> immedHi11_8;
143 Bitfield<3, 0> immedLo3_0;
144
145 Bitfield<15, 0> regList;
86
87 // Made up bitfields that make life easier.
88 Bitfield<33> sevenAndFour;
89 Bitfield<32> isMisc;
90
91 uint32_t instBits;
92
93 // All the different types of opcode fields.

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139
140 Bitfield<11, 0> immed11_0;
141 Bitfield<7, 0> immed7_0;
142
143 Bitfield<11, 8> immedHi11_8;
144 Bitfield<3, 0> immedLo3_0;
145
146 Bitfield<15, 0> regList;
146
147
147 Bitfield<23, 0> offset;
148 Bitfield<23, 0> offset;
148
149
149 Bitfield<23, 0> immed23_0;
150
151 Bitfield<11, 8> cpNum;
152 Bitfield<18, 16> fn;
153 Bitfield<14, 12> fd;
154 Bitfield<3> fpRegImm;
155 Bitfield<3, 0> fm;
156 Bitfield<2, 0> fpImm;

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208 class PCState : public GenericISA::UPCState<MachInst>
209 {
210 protected:
211
212 typedef GenericISA::UPCState<MachInst> Base;
213
214 enum FlagBits {
215 ThumbBit = (1 << 0),
150 Bitfield<23, 0> immed23_0;
151
152 Bitfield<11, 8> cpNum;
153 Bitfield<18, 16> fn;
154 Bitfield<14, 12> fd;
155 Bitfield<3> fpRegImm;
156 Bitfield<3, 0> fm;
157 Bitfield<2, 0> fpImm;

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209 class PCState : public GenericISA::UPCState<MachInst>
210 {
211 protected:
212
213 typedef GenericISA::UPCState<MachInst> Base;
214
215 enum FlagBits {
216 ThumbBit = (1 << 0),
216 JazelleBit = (1 << 1)
217 JazelleBit = (1 << 1),
218 AArch64Bit = (1 << 2)
217 };
218 uint8_t flags;
219 uint8_t nextFlags;
220 uint8_t _itstate;
221 uint8_t _nextItstate;
222 uint8_t _size;
223 public:
224 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0)

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299 nextJazelle(bool val)
300 {
301 if (val)
302 nextFlags |= JazelleBit;
303 else
304 nextFlags &= ~JazelleBit;
305 }
306
219 };
220 uint8_t flags;
221 uint8_t nextFlags;
222 uint8_t _itstate;
223 uint8_t _nextItstate;
224 uint8_t _size;
225 public:
226 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0)

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301 nextJazelle(bool val)
302 {
303 if (val)
304 nextFlags |= JazelleBit;
305 else
306 nextFlags &= ~JazelleBit;
307 }
308
309 bool
310 aarch64() const
311 {
312 return flags & AArch64Bit;
313 }
314
315 void
316 aarch64(bool val)
317 {
318 if (val)
319 flags |= AArch64Bit;
320 else
321 flags &= ~AArch64Bit;
322 }
323
324 bool
325 nextAArch64() const
326 {
327 return nextFlags & AArch64Bit;
328 }
329
330 void
331 nextAArch64(bool val)
332 {
333 if (val)
334 nextFlags |= AArch64Bit;
335 else
336 nextFlags &= ~AArch64Bit;
337 }
338
339
307 uint8_t
308 itstate() const
309 {
310 return _itstate;
311 }
312
313 void
314 itstate(uint8_t value)

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369
370 Addr
371 instPC() const
372 {
373 return pc() + (thumb() ? 4 : 8);
374 }
375
376 void
340 uint8_t
341 itstate() const
342 {
343 return _itstate;
344 }
345
346 void
347 itstate(uint8_t value)

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402
403 Addr
404 instPC() const
405 {
406 return pc() + (thumb() ? 4 : 8);
407 }
408
409 void
377 instNPC(uint32_t val)
410 instNPC(Addr val)
378 {
411 {
379 npc(val &~ mask(nextThumb() ? 1 : 2));
412 // @todo: review this when AArch32/64 interprocessing is
413 // supported
414 if (aarch64())
415 npc(val); // AArch64 doesn't force PC alignment, a PC
416 // Alignment Fault can be raised instead
417 else
418 npc(val &~ mask(nextThumb() ? 1 : 2));
380 }
381
382 Addr
383 instNPC() const
384 {
385 return npc();
386 }
387
388 // Perform an interworking branch.
389 void
419 }
420
421 Addr
422 instNPC() const
423 {
424 return npc();
425 }
426
427 // Perform an interworking branch.
428 void
390 instIWNPC(uint32_t val)
429 instIWNPC(Addr val)
391 {
392 bool thumbEE = (thumb() && jazelle());
393
394 Addr newPC = val;
395 if (thumbEE) {
396 if (bits(newPC, 0)) {
397 newPC = newPC & ~mask(1);
398 } // else we have a bad interworking address; do not call

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412 }
413 }
414 npc(newPC);
415 }
416
417 // Perform an interworking branch in ARM mode, a regular branch
418 // otherwise.
419 void
430 {
431 bool thumbEE = (thumb() && jazelle());
432
433 Addr newPC = val;
434 if (thumbEE) {
435 if (bits(newPC, 0)) {
436 newPC = newPC & ~mask(1);
437 } // else we have a bad interworking address; do not call

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451 }
452 }
453 npc(newPC);
454 }
455
456 // Perform an interworking branch in ARM mode, a regular branch
457 // otherwise.
458 void
420 instAIWNPC(uint32_t val)
459 instAIWNPC(Addr val)
421 {
422 if (!thumb() && !jazelle())
423 instIWNPC(val);
424 else
425 instNPC(val);
426 }
427
428 bool

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465 // Shift types for ARM instructions
466 enum ArmShiftType {
467 LSL = 0,
468 LSR,
469 ASR,
470 ROR
471 };
472
460 {
461 if (!thumb() && !jazelle())
462 instIWNPC(val);
463 else
464 instNPC(val);
465 }
466
467 bool

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504 // Shift types for ARM instructions
505 enum ArmShiftType {
506 LSL = 0,
507 LSR,
508 ASR,
509 ROR
510 };
511
512 // Extension types for ARM instructions
513 enum ArmExtendType {
514 UXTB = 0,
515 UXTH = 1,
516 UXTW = 2,
517 UXTX = 3,
518 SXTB = 4,
519 SXTH = 5,
520 SXTW = 6,
521 SXTX = 7
522 };
523
473 typedef uint64_t LargestRead;
474 // Need to use 64 bits to make sure that read requests get handled properly
475
476 typedef int RegContextParam;
477 typedef int RegContextVal;
478
479 //used in FP convert & round function
480 enum ConvertType{

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503 //used in FP convert & round function
504 enum RoundMode{
505 RND_ZERO,
506 RND_DOWN,
507 RND_UP,
508 RND_NEAREST
509 };
510
524 typedef uint64_t LargestRead;
525 // Need to use 64 bits to make sure that read requests get handled properly
526
527 typedef int RegContextParam;
528 typedef int RegContextVal;
529
530 //used in FP convert & round function
531 enum ConvertType{

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554 //used in FP convert & round function
555 enum RoundMode{
556 RND_ZERO,
557 RND_DOWN,
558 RND_UP,
559 RND_NEAREST
560 };
561
562 enum ExceptionLevel {
563 EL0 = 0,
564 EL1,
565 EL2,
566 EL3
567 };
568
511 enum OperatingMode {
569 enum OperatingMode {
570 MODE_EL0T = 0x0,
571 MODE_EL1T = 0x4,
572 MODE_EL1H = 0x5,
573 MODE_EL2T = 0x8,
574 MODE_EL2H = 0x9,
575 MODE_EL3T = 0xC,
576 MODE_EL3H = 0xD,
512 MODE_USER = 16,
513 MODE_FIQ = 17,
514 MODE_IRQ = 18,
515 MODE_SVC = 19,
516 MODE_MON = 22,
517 MODE_ABORT = 23,
577 MODE_USER = 16,
578 MODE_FIQ = 17,
579 MODE_IRQ = 18,
580 MODE_SVC = 19,
581 MODE_MON = 22,
582 MODE_ABORT = 23,
583 MODE_HYP = 26,
518 MODE_UNDEFINED = 27,
519 MODE_SYSTEM = 31,
520 MODE_MAXMODE = MODE_SYSTEM
521 };
522
584 MODE_UNDEFINED = 27,
585 MODE_SYSTEM = 31,
586 MODE_MAXMODE = MODE_SYSTEM
587 };
588
589 enum ExceptionClass {
590 EC_INVALID = -1,
591 EC_UNKNOWN = 0x0,
592 EC_TRAPPED_WFI_WFE = 0x1,
593 EC_TRAPPED_CP15_MCR_MRC = 0x3,
594 EC_TRAPPED_CP15_MCRR_MRRC = 0x4,
595 EC_TRAPPED_CP14_MCR_MRC = 0x5,
596 EC_TRAPPED_CP14_LDC_STC = 0x6,
597 EC_TRAPPED_HCPTR = 0x7,
598 EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias
599 EC_TRAPPED_CP10_MRC_VMRS = 0x8,
600 EC_TRAPPED_BXJ = 0xA,
601 EC_TRAPPED_CP14_MCRR_MRRC = 0xC,
602 EC_ILLEGAL_INST = 0xE,
603 EC_SVC_TO_HYP = 0x11,
604 EC_SVC = 0x11, // AArch64 alias
605 EC_HVC = 0x12,
606 EC_SMC_TO_HYP = 0x13,
607 EC_SMC = 0x13, // AArch64 alias
608 EC_SVC_64 = 0x15,
609 EC_HVC_64 = 0x16,
610 EC_SMC_64 = 0x17,
611 EC_TRAPPED_MSR_MRS_64 = 0x18,
612 EC_PREFETCH_ABORT_TO_HYP = 0x20,
613 EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias
614 EC_PREFETCH_ABORT_FROM_HYP = 0x21,
615 EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias
616 EC_PC_ALIGNMENT = 0x22,
617 EC_DATA_ABORT_TO_HYP = 0x24,
618 EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias
619 EC_DATA_ABORT_FROM_HYP = 0x25,
620 EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias
621 EC_STACK_PTR_ALIGNMENT = 0x26,
622 EC_FP_EXCEPTION = 0x28,
623 EC_FP_EXCEPTION_64 = 0x2C,
624 EC_SERROR = 0x2F
625 };
626
627 BitUnion8(OperatingMode64)
628 Bitfield<0> spX;
629 Bitfield<3, 2> el;
630 Bitfield<4> width;
631 EndBitUnion(OperatingMode64)
632
633 static bool inline
634 opModeIs64(OperatingMode mode)
635 {
636 return ((OperatingMode64)(uint8_t)mode).width == 0;
637 }
638
639 static bool inline
640 opModeIsH(OperatingMode mode)
641 {
642 return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H);
643 }
644
645 static bool inline
646 opModeIsT(OperatingMode mode)
647 {
648 return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T ||
649 mode == MODE_EL3T);
650 }
651
652 static ExceptionLevel inline
653 opModeToEL(OperatingMode mode)
654 {
655 bool aarch32 = ((mode >> 4) & 1) ? true : false;
656 if (aarch32) {
657 switch (mode) {
658 case MODE_USER:
659 return EL0;
660 case MODE_FIQ:
661 case MODE_IRQ:
662 case MODE_SVC:
663 case MODE_ABORT:
664 case MODE_UNDEFINED:
665 case MODE_SYSTEM:
666 return EL1;
667 case MODE_HYP:
668 return EL2;
669 case MODE_MON:
670 return EL3;
671 default:
672 panic("Invalid operating mode: %d", mode);
673 break;
674 }
675 } else {
676 // aarch64
677 return (ExceptionLevel) ((mode >> 2) & 3);
678 }
679 }
680
523 static inline bool
524 badMode(OperatingMode mode)
525 {
526 switch (mode) {
681 static inline bool
682 badMode(OperatingMode mode)
683 {
684 switch (mode) {
685 case MODE_EL0T:
686 case MODE_EL1T:
687 case MODE_EL1H:
688 case MODE_EL2T:
689 case MODE_EL2H:
690 case MODE_EL3T:
691 case MODE_EL3H:
527 case MODE_USER:
528 case MODE_FIQ:
529 case MODE_IRQ:
530 case MODE_SVC:
531 case MODE_MON:
532 case MODE_ABORT:
692 case MODE_USER:
693 case MODE_FIQ:
694 case MODE_IRQ:
695 case MODE_SVC:
696 case MODE_MON:
697 case MODE_ABORT:
698 case MODE_HYP:
533 case MODE_UNDEFINED:
534 case MODE_SYSTEM:
535 return false;
536 default:
537 return true;
538 }
539 }
540
699 case MODE_UNDEFINED:
700 case MODE_SYSTEM:
701 return false;
702 default:
703 return true;
704 }
705 }
706
707
708 static inline bool
709 badMode32(OperatingMode mode)
710 {
711 switch (mode) {
712 case MODE_USER:
713 case MODE_FIQ:
714 case MODE_IRQ:
715 case MODE_SVC:
716 case MODE_MON:
717 case MODE_ABORT:
718 case MODE_HYP:
719 case MODE_UNDEFINED:
720 case MODE_SYSTEM:
721 return false;
722 default:
723 return true;
724 }
725 }
726
541} // namespace ArmISA
542
543__hash_namespace_begin
544 template<>
545 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
546 size_t operator()(const ArmISA::ExtMachInst &emi) const {
547 return hash<uint32_t>::operator()((uint32_t)emi);
548 };
549 };
550__hash_namespace_end
551
552#endif
727} // namespace ArmISA
728
729__hash_namespace_begin
730 template<>
731 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
732 size_t operator()(const ArmISA::ExtMachInst &emi) const {
733 return hash<uint32_t>::operator()((uint32_t)emi);
734 };
735 };
736__hash_namespace_end
737
738#endif