types.hh (7680:f4eda002333b) types.hh (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
46#include "arch/generic/types.hh"
46#include "base/bitunion.hh"
47#include "base/hashmap.hh"
47#include "base/bitunion.hh"
48#include "base/hashmap.hh"
49#include "base/misc.hh"
48#include "base/types.hh"
49
50namespace ArmISA
51{
52 typedef uint32_t MachInst;
53
54 BitUnion64(ExtMachInst)
55 Bitfield<63, 56> newItstate;

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183 Bitfield<7, 6> ltopcode7_6;
184 Bitfield<7, 4> ltopcode7_4;
185 Bitfield<4> ltopcode4;
186
187 Bitfield<11, 8> ltrd;
188 Bitfield<11, 8> ltcoproc;
189 EndBitUnion(ExtMachInst)
190
50#include "base/types.hh"
51
52namespace ArmISA
53{
54 typedef uint32_t MachInst;
55
56 BitUnion64(ExtMachInst)
57 Bitfield<63, 56> newItstate;

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185 Bitfield<7, 6> ltopcode7_6;
186 Bitfield<7, 4> ltopcode7_4;
187 Bitfield<4> ltopcode4;
188
189 Bitfield<11, 8> ltrd;
190 Bitfield<11, 8> ltcoproc;
191 EndBitUnion(ExtMachInst)
192
193 class PCState : public GenericISA::UPCState<MachInst>
194 {
195 protected:
196
197 typedef GenericISA::UPCState<MachInst> Base;
198
199 enum FlagBits {
200 ThumbBit = (1 << 0),
201 JazelleBit = (1 << 1)
202 };
203 uint8_t flags;
204 uint8_t nextFlags;
205
206 public:
207 PCState() : flags(0), nextFlags(0)
208 {}
209
210 void
211 set(Addr val)
212 {
213 Base::set(val);
214 npc(val + (thumb() ? 2 : 4));
215 }
216
217 PCState(Addr val) : flags(0), nextFlags(0)
218 { set(val); }
219
220 bool
221 thumb() const
222 {
223 return flags & ThumbBit;
224 }
225
226 void
227 thumb(bool val)
228 {
229 if (val)
230 flags |= ThumbBit;
231 else
232 flags &= ~ThumbBit;
233 }
234
235 bool
236 nextThumb() const
237 {
238 return nextFlags & ThumbBit;
239 }
240
241 void
242 nextThumb(bool val)
243 {
244 if (val)
245 nextFlags |= ThumbBit;
246 else
247 nextFlags &= ~ThumbBit;
248 }
249
250 bool
251 jazelle() const
252 {
253 return flags & JazelleBit;
254 }
255
256 void
257 jazelle(bool val)
258 {
259 if (val)
260 flags |= JazelleBit;
261 else
262 flags &= ~JazelleBit;
263 }
264
265 bool
266 nextJazelle() const
267 {
268 return nextFlags & JazelleBit;
269 }
270
271 void
272 nextJazelle(bool val)
273 {
274 if (val)
275 nextFlags |= JazelleBit;
276 else
277 nextFlags &= ~JazelleBit;
278 }
279
280 void
281 advance()
282 {
283 Base::advance();
284 npc(pc() + (thumb() ? 2 : 4));
285 flags = nextFlags;
286 }
287
288 void
289 uEnd()
290 {
291 advance();
292 upc(0);
293 nupc(1);
294 }
295
296 Addr
297 instPC() const
298 {
299 return pc() + (thumb() ? 4 : 8);
300 }
301
302 void
303 instNPC(uint32_t val)
304 {
305 npc(val &~ mask(nextThumb() ? 1 : 2));
306 }
307
308 Addr
309 instNPC() const
310 {
311 return npc();
312 }
313
314 // Perform an interworking branch.
315 void
316 instIWNPC(uint32_t val)
317 {
318 bool thumbEE = (thumb() && jazelle());
319
320 Addr newPC = val;
321 if (thumbEE) {
322 if (bits(newPC, 0)) {
323 newPC = newPC & ~mask(1);
324 } else {
325 panic("Bad thumbEE interworking branch address %#x.\n",
326 newPC);
327 }
328 } else {
329 if (bits(newPC, 0)) {
330 nextThumb(true);
331 newPC = newPC & ~mask(1);
332 } else if (!bits(newPC, 1)) {
333 nextThumb(false);
334 } else {
335 warn("Bad interworking branch address %#x.\n", newPC);
336 }
337 }
338 npc(newPC);
339 }
340
341 // Perform an interworking branch in ARM mode, a regular branch
342 // otherwise.
343 void
344 instAIWNPC(uint32_t val)
345 {
346 if (!thumb() && !jazelle())
347 instIWNPC(val);
348 else
349 instNPC(val);
350 }
351
352 bool
353 operator == (const PCState &opc) const
354 {
355 return Base::operator == (opc) &&
356 flags == opc.flags && nextFlags == opc.nextFlags;
357 }
358
359 void
360 serialize(std::ostream &os)
361 {
362 Base::serialize(os);
363 SERIALIZE_SCALAR(flags);
364 SERIALIZE_SCALAR(nextFlags);
365 }
366
367 void
368 unserialize(Checkpoint *cp, const std::string &section)
369 {
370 Base::unserialize(cp, section);
371 UNSERIALIZE_SCALAR(flags);
372 UNSERIALIZE_SCALAR(nextFlags);
373 }
374 };
375
191 // Shift types for ARM instructions
192 enum ArmShiftType {
193 LSL = 0,
194 LSR,
195 ASR,
196 ROR
197 };
198

--- 84 unchanged lines hidden --- 		376 // Shift types for ARM instructions
377 enum ArmShiftType {
378 LSL = 0,
379 LSR,
380 ASR,
381 ROR
382 };
383

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