types.hh (12732:c8b4f25eea9b) types.hh (12763:37c243ed1112)
1/*
1/*
2 * Copyright (c) 2010, 2012-2013, 2017 ARM Limited
2 * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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65 // Bitfields for moving to/from CPSR
66 Bitfield<7, 2> top6;
67 Bitfield<1, 0> bottom2;
68 EndBitUnion(ITSTATE)
69
70 BitUnion64(ExtMachInst)
71 // Decoder state
72 Bitfield<63, 62> decoderFault; // See DecoderFault
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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65 // Bitfields for moving to/from CPSR
66 Bitfield<7, 2> top6;
67 Bitfield<1, 0> bottom2;
68 EndBitUnion(ITSTATE)
69
70 BitUnion64(ExtMachInst)
71 // Decoder state
72 Bitfield<63, 62> decoderFault; // See DecoderFault
73 Bitfield<61> illegalExecution;
73
74 // ITSTATE bits
75 Bitfield<55, 48> itstate;
76 Bitfield<55, 52> itstateCond;
77 Bitfield<51, 48> itstateMask;
78
79 // FPSCR fields
80 Bitfield<41, 40> fpscrStride;

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213
214 typedef GenericISA::UPCState<MachInst> Base;
215
216 enum FlagBits {
217 ThumbBit = (1 << 0),
218 JazelleBit = (1 << 1),
219 AArch64Bit = (1 << 2)
220 };
74
75 // ITSTATE bits
76 Bitfield<55, 48> itstate;
77 Bitfield<55, 52> itstateCond;
78 Bitfield<51, 48> itstateMask;
79
80 // FPSCR fields
81 Bitfield<41, 40> fpscrStride;

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214
215 typedef GenericISA::UPCState<MachInst> Base;
216
217 enum FlagBits {
218 ThumbBit = (1 << 0),
219 JazelleBit = (1 << 1),
220 AArch64Bit = (1 << 2)
221 };
222
221 uint8_t flags;
222 uint8_t nextFlags;
223 uint8_t _itstate;
224 uint8_t _nextItstate;
225 uint8_t _size;
223 uint8_t flags;
224 uint8_t nextFlags;
225 uint8_t _itstate;
226 uint8_t _nextItstate;
227 uint8_t _size;
228 bool _illegalExec;
226 public:
227 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
229 public:
230 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
228 _size(0)
231 _size(0), _illegalExec(false)
229 {}
230
231 void
232 set(Addr val)
233 {
234 Base::set(val);
235 npc(val + (thumb() ? 2 : 4));
236 }
237
238 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
232 {}
233
234 void
235 set(Addr val)
236 {
237 Base::set(val);
238 npc(val + (thumb() ? 2 : 4));
239 }
240
241 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
239 _nextItstate(0), _size(0)
242 _nextItstate(0), _size(0), _illegalExec(false)
240 { set(val); }
241
242 bool
243 { set(val); }
244
245 bool
246 illegalExec() const
247 {
248 return _illegalExec;
249 }
250
251 void
252 illegalExec(bool val)
253 {
254 _illegalExec = val;
255 }
256
257 bool
243 thumb() const
244 {
245 return flags & ThumbBit;
246 }
247
248 void
249 thumb(bool val)
250 {

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467 instNPC(val);
468 }
469
470 bool
471 operator == (const PCState &opc) const
472 {
473 return Base::operator == (opc) &&
474 flags == opc.flags && nextFlags == opc.nextFlags &&
258 thumb() const
259 {
260 return flags & ThumbBit;
261 }
262
263 void
264 thumb(bool val)
265 {

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482 instNPC(val);
483 }
484
485 bool
486 operator == (const PCState &opc) const
487 {
488 return Base::operator == (opc) &&
489 flags == opc.flags && nextFlags == opc.nextFlags &&
475 _itstate == opc._itstate && _nextItstate == opc._nextItstate;
490 _itstate == opc._itstate &&
491 _nextItstate == opc._nextItstate &&
492 _illegalExec == opc._illegalExec;
476 }
477
478 bool
479 operator != (const PCState &opc) const
480 {
481 return !(*this == opc);
482 }
483
484 void
485 serialize(CheckpointOut &cp) const override
486 {
487 Base::serialize(cp);
488 SERIALIZE_SCALAR(flags);
489 SERIALIZE_SCALAR(_size);
490 SERIALIZE_SCALAR(nextFlags);
491 SERIALIZE_SCALAR(_itstate);
492 SERIALIZE_SCALAR(_nextItstate);
493 }
494
495 bool
496 operator != (const PCState &opc) const
497 {
498 return !(*this == opc);
499 }
500
501 void
502 serialize(CheckpointOut &cp) const override
503 {
504 Base::serialize(cp);
505 SERIALIZE_SCALAR(flags);
506 SERIALIZE_SCALAR(_size);
507 SERIALIZE_SCALAR(nextFlags);
508 SERIALIZE_SCALAR(_itstate);
509 SERIALIZE_SCALAR(_nextItstate);
510 SERIALIZE_SCALAR(_illegalExec);
493 }
494
495 void
496 unserialize(CheckpointIn &cp) override
497 {
498 Base::unserialize(cp);
499 UNSERIALIZE_SCALAR(flags);
500 UNSERIALIZE_SCALAR(_size);
501 UNSERIALIZE_SCALAR(nextFlags);
502 UNSERIALIZE_SCALAR(_itstate);
503 UNSERIALIZE_SCALAR(_nextItstate);
511 }
512
513 void
514 unserialize(CheckpointIn &cp) override
515 {
516 Base::unserialize(cp);
517 UNSERIALIZE_SCALAR(flags);
518 UNSERIALIZE_SCALAR(_size);
519 UNSERIALIZE_SCALAR(nextFlags);
520 UNSERIALIZE_SCALAR(_itstate);
521 UNSERIALIZE_SCALAR(_nextItstate);
522 UNSERIALIZE_SCALAR(_illegalExec);
504 }
505 };
506
507 // Shift types for ARM instructions
508 enum ArmShiftType {
509 LSL = 0,
510 LSR,
511 ASR,

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524 };
525
526 // Shift types for ARM instructions
527 enum ArmShiftType {
528 LSL = 0,
529 LSR,
530 ASR,

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