1/* |
2 * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 54 unchanged lines hidden (view full) --- 65 // Bitfields for moving to/from CPSR 66 Bitfield<7, 2> top6; 67 Bitfield<1, 0> bottom2; 68 EndBitUnion(ITSTATE) 69 70 BitUnion64(ExtMachInst) 71 // Decoder state 72 Bitfield<63, 62> decoderFault; // See DecoderFault |
73 Bitfield<61> illegalExecution; |
74 75 // ITSTATE bits 76 Bitfield<55, 48> itstate; 77 Bitfield<55, 52> itstateCond; 78 Bitfield<51, 48> itstateMask; 79 80 // FPSCR fields 81 Bitfield<41, 40> fpscrStride; --- 132 unchanged lines hidden (view full) --- 214 215 typedef GenericISA::UPCState<MachInst> Base; 216 217 enum FlagBits { 218 ThumbBit = (1 << 0), 219 JazelleBit = (1 << 1), 220 AArch64Bit = (1 << 2) 221 }; |
222 |
223 uint8_t flags; 224 uint8_t nextFlags; 225 uint8_t _itstate; 226 uint8_t _nextItstate; 227 uint8_t _size; |
228 bool _illegalExec; |
229 public: 230 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0), |
231 _size(0), _illegalExec(false) |
232 {} 233 234 void 235 set(Addr val) 236 { 237 Base::set(val); 238 npc(val + (thumb() ? 2 : 4)); 239 } 240 241 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), |
242 _nextItstate(0), _size(0), _illegalExec(false) |
243 { set(val); } 244 245 bool |
246 illegalExec() const 247 { 248 return _illegalExec; 249 } 250 251 void 252 illegalExec(bool val) 253 { 254 _illegalExec = val; 255 } 256 257 bool |
258 thumb() const 259 { 260 return flags & ThumbBit; 261 } 262 263 void 264 thumb(bool val) 265 { --- 216 unchanged lines hidden (view full) --- 482 instNPC(val); 483 } 484 485 bool 486 operator == (const PCState &opc) const 487 { 488 return Base::operator == (opc) && 489 flags == opc.flags && nextFlags == opc.nextFlags && |
490 _itstate == opc._itstate && 491 _nextItstate == opc._nextItstate && 492 _illegalExec == opc._illegalExec; |
493 } 494 495 bool 496 operator != (const PCState &opc) const 497 { 498 return !(*this == opc); 499 } 500 501 void 502 serialize(CheckpointOut &cp) const override 503 { 504 Base::serialize(cp); 505 SERIALIZE_SCALAR(flags); 506 SERIALIZE_SCALAR(_size); 507 SERIALIZE_SCALAR(nextFlags); 508 SERIALIZE_SCALAR(_itstate); 509 SERIALIZE_SCALAR(_nextItstate); |
510 SERIALIZE_SCALAR(_illegalExec); |
511 } 512 513 void 514 unserialize(CheckpointIn &cp) override 515 { 516 Base::unserialize(cp); 517 UNSERIALIZE_SCALAR(flags); 518 UNSERIALIZE_SCALAR(_size); 519 UNSERIALIZE_SCALAR(nextFlags); 520 UNSERIALIZE_SCALAR(_itstate); 521 UNSERIALIZE_SCALAR(_nextItstate); |
522 UNSERIALIZE_SCALAR(_illegalExec); |
523 } 524 }; 525 526 // Shift types for ARM instructions 527 enum ArmShiftType { 528 LSL = 0, 529 LSR, 530 ASR, --- 230 unchanged lines hidden --- |