1/* 2 * Copyright (c) 2010, 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 54 unchanged lines hidden (view full) --- 63 */ 64 Bitfield<7, 4> cond; 65 Bitfield<3, 0> mask; 66 // Bitfields for moving to/from CPSR 67 Bitfield<7, 2> top6; 68 Bitfield<1, 0> bottom2; 69 EndBitUnion(ITSTATE) 70 |
71 BitUnion64(ExtMachInst) |
72 // Decoder state 73 Bitfield<63, 62> decoderFault; // See DecoderFault 74 |
75 // ITSTATE bits 76 Bitfield<55, 48> itstate; 77 Bitfield<55, 52> itstateCond; 78 Bitfield<51, 48> itstateMask; 79 80 // FPSCR fields 81 Bitfield<41, 40> fpscrStride; 82 Bitfield<39, 37> fpscrLen; --- 540 unchanged lines hidden (view full) --- 623 EC_DATA_ABORT_FROM_HYP = 0x25, 624 EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias 625 EC_STACK_PTR_ALIGNMENT = 0x26, 626 EC_FP_EXCEPTION = 0x28, 627 EC_FP_EXCEPTION_64 = 0x2C, 628 EC_SERROR = 0x2F 629 }; 630 |
631 /** 632 * Instruction decoder fault codes in ExtMachInst. 633 */ 634 enum DecoderFault : std::uint8_t { 635 OK = 0x0, ///< No fault 636 UNALIGNED = 0x1, ///< Unaligned instruction fault 637 638 PANIC = 0x3, ///< Internal gem5 error 639 }; 640 |
641 BitUnion8(OperatingMode64) 642 Bitfield<0> spX; 643 Bitfield<3, 2> el; 644 Bitfield<4> width; 645 EndBitUnion(OperatingMode64) 646 647 static bool inline 648 opModeIs64(OperatingMode mode) --- 109 unchanged lines hidden --- |