1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
46#include "arch/generic/types.hh"
47#include "base/bitunion.hh"
48#include "base/hashmap.hh"
49#include "base/misc.hh"
50#include "base/types.hh"
51
52namespace ArmISA
53{
54 typedef uint32_t MachInst;
55
56 BitUnion64(ExtMachInst)
57 Bitfield<63, 56> newItstate;
58 // ITSTATE bits
59 Bitfield<55, 48> itstate;
60 Bitfield<55, 52> itstateCond;
61 Bitfield<51, 48> itstateMask;
62
63 // FPSCR fields
64 Bitfield<41, 40> fpscrStride;
65 Bitfield<39, 37> fpscrLen;
66
67 // Bitfields to select mode.
68 Bitfield<36> thumb;
69 Bitfield<35> bigThumb;
70
71 // Made up bitfields that make life easier.
72 Bitfield<33> sevenAndFour;
73 Bitfield<32> isMisc;
74
75 uint32_t instBits;
76
77 // All the different types of opcode fields.
78 Bitfield<27, 25> encoding;
79 Bitfield<25> useImm;
80 Bitfield<24, 21> opcode;
81 Bitfield<24, 20> mediaOpcode;
82 Bitfield<24> opcode24;
83 Bitfield<24, 23> opcode24_23;
84 Bitfield<23, 20> opcode23_20;
85 Bitfield<23, 21> opcode23_21;
86 Bitfield<20> opcode20;
87 Bitfield<22> opcode22;
88 Bitfield<19, 16> opcode19_16;
89 Bitfield<19> opcode19;
90 Bitfield<18> opcode18;
91 Bitfield<15, 12> opcode15_12;
92 Bitfield<15> opcode15;
93 Bitfield<7, 4> miscOpcode;
94 Bitfield<7,5> opc2;
95 Bitfield<7> opcode7;
96 Bitfield<6> opcode6;
97 Bitfield<4> opcode4;
98
99 Bitfield<31, 28> condCode;
100 Bitfield<20> sField;
101 Bitfield<19, 16> rn;
102 Bitfield<15, 12> rd;
103 Bitfield<15, 12> rt;
104 Bitfield<11, 7> shiftSize;
105 Bitfield<6, 5> shift;
106 Bitfield<3, 0> rm;
107
108 Bitfield<11, 8> rs;
109
110 SubBitUnion(puswl, 24, 20)
111 Bitfield<24> prepost;
112 Bitfield<23> up;
113 Bitfield<22> psruser;
114 Bitfield<21> writeback;
115 Bitfield<20> loadOp;
116 EndSubBitUnion(puswl)
117
118 Bitfield<24, 20> pubwl;
119
120 Bitfield<7, 0> imm;
121
122 Bitfield<11, 8> rotate;
123
124 Bitfield<11, 0> immed11_0;
125 Bitfield<7, 0> immed7_0;
126
127 Bitfield<11, 8> immedHi11_8;
128 Bitfield<3, 0> immedLo3_0;
129
130 Bitfield<15, 0> regList;
131
132 Bitfield<23, 0> offset;
133
134 Bitfield<23, 0> immed23_0;
135
136 Bitfield<11, 8> cpNum;
137 Bitfield<18, 16> fn;
138 Bitfield<14, 12> fd;
139 Bitfield<3> fpRegImm;
140 Bitfield<3, 0> fm;
141 Bitfield<2, 0> fpImm;
142 Bitfield<24, 20> punwl;
143
144 Bitfield<15, 8> m5Func;
145
146 // 16 bit thumb bitfields
147 Bitfield<15, 13> topcode15_13;
148 Bitfield<13, 11> topcode13_11;
149 Bitfield<12, 11> topcode12_11;
150 Bitfield<12, 10> topcode12_10;
151 Bitfield<11, 9> topcode11_9;
152 Bitfield<11, 8> topcode11_8;
153 Bitfield<10, 9> topcode10_9;
154 Bitfield<10, 8> topcode10_8;
155 Bitfield<9, 6> topcode9_6;
156 Bitfield<7> topcode7;
157 Bitfield<7, 6> topcode7_6;
158 Bitfield<7, 5> topcode7_5;
159 Bitfield<7, 4> topcode7_4;
160 Bitfield<3, 0> topcode3_0;
161
162 // 32 bit thumb bitfields
163 Bitfield<28, 27> htopcode12_11;
164 Bitfield<26, 25> htopcode10_9;
165 Bitfield<25> htopcode9;
166 Bitfield<25, 24> htopcode9_8;
167 Bitfield<25, 21> htopcode9_5;
168 Bitfield<25, 20> htopcode9_4;
169 Bitfield<24> htopcode8;
170 Bitfield<24, 23> htopcode8_7;
171 Bitfield<24, 22> htopcode8_6;
172 Bitfield<24, 21> htopcode8_5;
173 Bitfield<23> htopcode7;
174 Bitfield<23, 21> htopcode7_5;
175 Bitfield<22> htopcode6;
176 Bitfield<22, 21> htopcode6_5;
177 Bitfield<21, 20> htopcode5_4;
178 Bitfield<20> htopcode4;
179
180 Bitfield<19, 16> htrn;
181 Bitfield<20> hts;
182
183 Bitfield<15> ltopcode15;
184 Bitfield<11, 8> ltopcode11_8;
185 Bitfield<7, 6> ltopcode7_6;
186 Bitfield<7, 4> ltopcode7_4;
187 Bitfield<4> ltopcode4;
188
189 Bitfield<11, 8> ltrd;
190 Bitfield<11, 8> ltcoproc;
191 EndBitUnion(ExtMachInst)
192
193 class PCState : public GenericISA::UPCState<MachInst>
194 {
195 protected:
196
197 typedef GenericISA::UPCState<MachInst> Base;
198
199 enum FlagBits {
200 ThumbBit = (1 << 0),
201 JazelleBit = (1 << 1)
202 };
203 uint8_t flags;
204 uint8_t nextFlags;
205 uint8_t forcedItStateValue;
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
46#include "arch/generic/types.hh"
47#include "base/bitunion.hh"
48#include "base/hashmap.hh"
49#include "base/misc.hh"
50#include "base/types.hh"
51
52namespace ArmISA
53{
54 typedef uint32_t MachInst;
55
56 BitUnion64(ExtMachInst)
57 Bitfield<63, 56> newItstate;
58 // ITSTATE bits
59 Bitfield<55, 48> itstate;
60 Bitfield<55, 52> itstateCond;
61 Bitfield<51, 48> itstateMask;
62
63 // FPSCR fields
64 Bitfield<41, 40> fpscrStride;
65 Bitfield<39, 37> fpscrLen;
66
67 // Bitfields to select mode.
68 Bitfield<36> thumb;
69 Bitfield<35> bigThumb;
70
71 // Made up bitfields that make life easier.
72 Bitfield<33> sevenAndFour;
73 Bitfield<32> isMisc;
74
75 uint32_t instBits;
76
77 // All the different types of opcode fields.
78 Bitfield<27, 25> encoding;
79 Bitfield<25> useImm;
80 Bitfield<24, 21> opcode;
81 Bitfield<24, 20> mediaOpcode;
82 Bitfield<24> opcode24;
83 Bitfield<24, 23> opcode24_23;
84 Bitfield<23, 20> opcode23_20;
85 Bitfield<23, 21> opcode23_21;
86 Bitfield<20> opcode20;
87 Bitfield<22> opcode22;
88 Bitfield<19, 16> opcode19_16;
89 Bitfield<19> opcode19;
90 Bitfield<18> opcode18;
91 Bitfield<15, 12> opcode15_12;
92 Bitfield<15> opcode15;
93 Bitfield<7, 4> miscOpcode;
94 Bitfield<7,5> opc2;
95 Bitfield<7> opcode7;
96 Bitfield<6> opcode6;
97 Bitfield<4> opcode4;
98
99 Bitfield<31, 28> condCode;
100 Bitfield<20> sField;
101 Bitfield<19, 16> rn;
102 Bitfield<15, 12> rd;
103 Bitfield<15, 12> rt;
104 Bitfield<11, 7> shiftSize;
105 Bitfield<6, 5> shift;
106 Bitfield<3, 0> rm;
107
108 Bitfield<11, 8> rs;
109
110 SubBitUnion(puswl, 24, 20)
111 Bitfield<24> prepost;
112 Bitfield<23> up;
113 Bitfield<22> psruser;
114 Bitfield<21> writeback;
115 Bitfield<20> loadOp;
116 EndSubBitUnion(puswl)
117
118 Bitfield<24, 20> pubwl;
119
120 Bitfield<7, 0> imm;
121
122 Bitfield<11, 8> rotate;
123
124 Bitfield<11, 0> immed11_0;
125 Bitfield<7, 0> immed7_0;
126
127 Bitfield<11, 8> immedHi11_8;
128 Bitfield<3, 0> immedLo3_0;
129
130 Bitfield<15, 0> regList;
131
132 Bitfield<23, 0> offset;
133
134 Bitfield<23, 0> immed23_0;
135
136 Bitfield<11, 8> cpNum;
137 Bitfield<18, 16> fn;
138 Bitfield<14, 12> fd;
139 Bitfield<3> fpRegImm;
140 Bitfield<3, 0> fm;
141 Bitfield<2, 0> fpImm;
142 Bitfield<24, 20> punwl;
143
144 Bitfield<15, 8> m5Func;
145
146 // 16 bit thumb bitfields
147 Bitfield<15, 13> topcode15_13;
148 Bitfield<13, 11> topcode13_11;
149 Bitfield<12, 11> topcode12_11;
150 Bitfield<12, 10> topcode12_10;
151 Bitfield<11, 9> topcode11_9;
152 Bitfield<11, 8> topcode11_8;
153 Bitfield<10, 9> topcode10_9;
154 Bitfield<10, 8> topcode10_8;
155 Bitfield<9, 6> topcode9_6;
156 Bitfield<7> topcode7;
157 Bitfield<7, 6> topcode7_6;
158 Bitfield<7, 5> topcode7_5;
159 Bitfield<7, 4> topcode7_4;
160 Bitfield<3, 0> topcode3_0;
161
162 // 32 bit thumb bitfields
163 Bitfield<28, 27> htopcode12_11;
164 Bitfield<26, 25> htopcode10_9;
165 Bitfield<25> htopcode9;
166 Bitfield<25, 24> htopcode9_8;
167 Bitfield<25, 21> htopcode9_5;
168 Bitfield<25, 20> htopcode9_4;
169 Bitfield<24> htopcode8;
170 Bitfield<24, 23> htopcode8_7;
171 Bitfield<24, 22> htopcode8_6;
172 Bitfield<24, 21> htopcode8_5;
173 Bitfield<23> htopcode7;
174 Bitfield<23, 21> htopcode7_5;
175 Bitfield<22> htopcode6;
176 Bitfield<22, 21> htopcode6_5;
177 Bitfield<21, 20> htopcode5_4;
178 Bitfield<20> htopcode4;
179
180 Bitfield<19, 16> htrn;
181 Bitfield<20> hts;
182
183 Bitfield<15> ltopcode15;
184 Bitfield<11, 8> ltopcode11_8;
185 Bitfield<7, 6> ltopcode7_6;
186 Bitfield<7, 4> ltopcode7_4;
187 Bitfield<4> ltopcode4;
188
189 Bitfield<11, 8> ltrd;
190 Bitfield<11, 8> ltcoproc;
191 EndBitUnion(ExtMachInst)
192
193 class PCState : public GenericISA::UPCState<MachInst>
194 {
195 protected:
196
197 typedef GenericISA::UPCState<MachInst> Base;
198
199 enum FlagBits {
200 ThumbBit = (1 << 0),
201 JazelleBit = (1 << 1)
202 };
203 uint8_t flags;
204 uint8_t nextFlags;
205 uint8_t forcedItStateValue;
|
405 UNSERIALIZE_SCALAR(nextFlags);
406 UNSERIALIZE_SCALAR(forcedItStateValue);
407 UNSERIALIZE_SCALAR(forcedItStateValid);
408 }
409 };
410
411 // Shift types for ARM instructions
412 enum ArmShiftType {
413 LSL = 0,
414 LSR,
415 ASR,
416 ROR
417 };
418
419 typedef uint64_t LargestRead;
420 // Need to use 64 bits to make sure that read requests get handled properly
421
422 typedef int RegContextParam;
423 typedef int RegContextVal;
424
425 //used in FP convert & round function
426 enum ConvertType{
427 SINGLE_TO_DOUBLE,
428 SINGLE_TO_WORD,
429 SINGLE_TO_LONG,
430
431 DOUBLE_TO_SINGLE,
432 DOUBLE_TO_WORD,
433 DOUBLE_TO_LONG,
434
435 LONG_TO_SINGLE,
436 LONG_TO_DOUBLE,
437 LONG_TO_WORD,
438 LONG_TO_PS,
439
440 WORD_TO_SINGLE,
441 WORD_TO_DOUBLE,
442 WORD_TO_LONG,
443 WORD_TO_PS,
444
445 PL_TO_SINGLE,
446 PU_TO_SINGLE
447 };
448
449 //used in FP convert & round function
450 enum RoundMode{
451 RND_ZERO,
452 RND_DOWN,
453 RND_UP,
454 RND_NEAREST
455 };
456
457 enum OperatingMode {
458 MODE_USER = 16,
459 MODE_FIQ = 17,
460 MODE_IRQ = 18,
461 MODE_SVC = 19,
462 MODE_MON = 22,
463 MODE_ABORT = 23,
464 MODE_UNDEFINED = 27,
465 MODE_SYSTEM = 31,
466 MODE_MAXMODE = MODE_SYSTEM
467 };
468
469 static inline bool
470 badMode(OperatingMode mode)
471 {
472 switch (mode) {
473 case MODE_USER:
474 case MODE_FIQ:
475 case MODE_IRQ:
476 case MODE_SVC:
477 case MODE_MON:
478 case MODE_ABORT:
479 case MODE_UNDEFINED:
480 case MODE_SYSTEM:
481 return false;
482 default:
483 return true;
484 }
485 }
486
487 struct CoreSpecific {
488 // Empty for now on the ARM
489 };
490
491} // namespace ArmISA
492
493namespace __hash_namespace {
494 template<>
495 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
496 size_t operator()(const ArmISA::ExtMachInst &emi) const {
497 return hash<uint32_t>::operator()((uint32_t)emi);
498 };
499 };
500}
501
502#endif
| 418 UNSERIALIZE_SCALAR(nextFlags);
419 UNSERIALIZE_SCALAR(forcedItStateValue);
420 UNSERIALIZE_SCALAR(forcedItStateValid);
421 }
422 };
423
424 // Shift types for ARM instructions
425 enum ArmShiftType {
426 LSL = 0,
427 LSR,
428 ASR,
429 ROR
430 };
431
432 typedef uint64_t LargestRead;
433 // Need to use 64 bits to make sure that read requests get handled properly
434
435 typedef int RegContextParam;
436 typedef int RegContextVal;
437
438 //used in FP convert & round function
439 enum ConvertType{
440 SINGLE_TO_DOUBLE,
441 SINGLE_TO_WORD,
442 SINGLE_TO_LONG,
443
444 DOUBLE_TO_SINGLE,
445 DOUBLE_TO_WORD,
446 DOUBLE_TO_LONG,
447
448 LONG_TO_SINGLE,
449 LONG_TO_DOUBLE,
450 LONG_TO_WORD,
451 LONG_TO_PS,
452
453 WORD_TO_SINGLE,
454 WORD_TO_DOUBLE,
455 WORD_TO_LONG,
456 WORD_TO_PS,
457
458 PL_TO_SINGLE,
459 PU_TO_SINGLE
460 };
461
462 //used in FP convert & round function
463 enum RoundMode{
464 RND_ZERO,
465 RND_DOWN,
466 RND_UP,
467 RND_NEAREST
468 };
469
470 enum OperatingMode {
471 MODE_USER = 16,
472 MODE_FIQ = 17,
473 MODE_IRQ = 18,
474 MODE_SVC = 19,
475 MODE_MON = 22,
476 MODE_ABORT = 23,
477 MODE_UNDEFINED = 27,
478 MODE_SYSTEM = 31,
479 MODE_MAXMODE = MODE_SYSTEM
480 };
481
482 static inline bool
483 badMode(OperatingMode mode)
484 {
485 switch (mode) {
486 case MODE_USER:
487 case MODE_FIQ:
488 case MODE_IRQ:
489 case MODE_SVC:
490 case MODE_MON:
491 case MODE_ABORT:
492 case MODE_UNDEFINED:
493 case MODE_SYSTEM:
494 return false;
495 default:
496 return true;
497 }
498 }
499
500 struct CoreSpecific {
501 // Empty for now on the ARM
502 };
503
504} // namespace ArmISA
505
506namespace __hash_namespace {
507 template<>
508 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
509 size_t operator()(const ArmISA::ExtMachInst &emi) const {
510 return hash<uint32_t>::operator()((uint32_t)emi);
511 };
512 };
513}
514
515#endif
|