1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
46#include "arch/generic/types.hh"
47#include "base/bitunion.hh"
48#include "base/hashmap.hh"
49#include "base/misc.hh"
50#include "base/types.hh"
51
52namespace ArmISA
53{
54 typedef uint32_t MachInst;
55
56 BitUnion64(ExtMachInst)
57 Bitfield<63, 56> newItstate;
58 // ITSTATE bits
59 Bitfield<55, 48> itstate;
60 Bitfield<55, 52> itstateCond;
61 Bitfield<51, 48> itstateMask;
62
63 // FPSCR fields
64 Bitfield<41, 40> fpscrStride;
65 Bitfield<39, 37> fpscrLen;
66
67 // Bitfields to select mode.
68 Bitfield<36> thumb;
69 Bitfield<35> bigThumb;
70
71 // Made up bitfields that make life easier.
72 Bitfield<33> sevenAndFour;
73 Bitfield<32> isMisc;
74
75 uint32_t instBits;
76
77 // All the different types of opcode fields.
78 Bitfield<27, 25> encoding;
79 Bitfield<25> useImm;
80 Bitfield<24, 21> opcode;
81 Bitfield<24, 20> mediaOpcode;
82 Bitfield<24> opcode24;
83 Bitfield<24, 23> opcode24_23;
84 Bitfield<23, 20> opcode23_20;
85 Bitfield<23, 21> opcode23_21;
86 Bitfield<20> opcode20;
87 Bitfield<22> opcode22;
88 Bitfield<19, 16> opcode19_16;
89 Bitfield<19> opcode19;
90 Bitfield<18> opcode18;
91 Bitfield<15, 12> opcode15_12;
92 Bitfield<15> opcode15;
93 Bitfield<7, 4> miscOpcode;
94 Bitfield<7,5> opc2;
95 Bitfield<7> opcode7;
96 Bitfield<6> opcode6;
97 Bitfield<4> opcode4;
98
99 Bitfield<31, 28> condCode;
100 Bitfield<20> sField;
101 Bitfield<19, 16> rn;
102 Bitfield<15, 12> rd;
103 Bitfield<15, 12> rt;
104 Bitfield<11, 7> shiftSize;
105 Bitfield<6, 5> shift;
106 Bitfield<3, 0> rm;
107
108 Bitfield<11, 8> rs;
109
110 SubBitUnion(puswl, 24, 20)
111 Bitfield<24> prepost;
112 Bitfield<23> up;
113 Bitfield<22> psruser;
114 Bitfield<21> writeback;
115 Bitfield<20> loadOp;
116 EndSubBitUnion(puswl)
117
118 Bitfield<24, 20> pubwl;
119
120 Bitfield<7, 0> imm;
121
122 Bitfield<11, 8> rotate;
123
124 Bitfield<11, 0> immed11_0;
125 Bitfield<7, 0> immed7_0;
126
127 Bitfield<11, 8> immedHi11_8;
128 Bitfield<3, 0> immedLo3_0;
129
130 Bitfield<15, 0> regList;
131
132 Bitfield<23, 0> offset;
133
134 Bitfield<23, 0> immed23_0;
135
136 Bitfield<11, 8> cpNum;
137 Bitfield<18, 16> fn;
138 Bitfield<14, 12> fd;
139 Bitfield<3> fpRegImm;
140 Bitfield<3, 0> fm;
141 Bitfield<2, 0> fpImm;
142 Bitfield<24, 20> punwl;
143
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
46#include "arch/generic/types.hh"
47#include "base/bitunion.hh"
48#include "base/hashmap.hh"
49#include "base/misc.hh"
50#include "base/types.hh"
51
52namespace ArmISA
53{
54 typedef uint32_t MachInst;
55
56 BitUnion64(ExtMachInst)
57 Bitfield<63, 56> newItstate;
58 // ITSTATE bits
59 Bitfield<55, 48> itstate;
60 Bitfield<55, 52> itstateCond;
61 Bitfield<51, 48> itstateMask;
62
63 // FPSCR fields
64 Bitfield<41, 40> fpscrStride;
65 Bitfield<39, 37> fpscrLen;
66
67 // Bitfields to select mode.
68 Bitfield<36> thumb;
69 Bitfield<35> bigThumb;
70
71 // Made up bitfields that make life easier.
72 Bitfield<33> sevenAndFour;
73 Bitfield<32> isMisc;
74
75 uint32_t instBits;
76
77 // All the different types of opcode fields.
78 Bitfield<27, 25> encoding;
79 Bitfield<25> useImm;
80 Bitfield<24, 21> opcode;
81 Bitfield<24, 20> mediaOpcode;
82 Bitfield<24> opcode24;
83 Bitfield<24, 23> opcode24_23;
84 Bitfield<23, 20> opcode23_20;
85 Bitfield<23, 21> opcode23_21;
86 Bitfield<20> opcode20;
87 Bitfield<22> opcode22;
88 Bitfield<19, 16> opcode19_16;
89 Bitfield<19> opcode19;
90 Bitfield<18> opcode18;
91 Bitfield<15, 12> opcode15_12;
92 Bitfield<15> opcode15;
93 Bitfield<7, 4> miscOpcode;
94 Bitfield<7,5> opc2;
95 Bitfield<7> opcode7;
96 Bitfield<6> opcode6;
97 Bitfield<4> opcode4;
98
99 Bitfield<31, 28> condCode;
100 Bitfield<20> sField;
101 Bitfield<19, 16> rn;
102 Bitfield<15, 12> rd;
103 Bitfield<15, 12> rt;
104 Bitfield<11, 7> shiftSize;
105 Bitfield<6, 5> shift;
106 Bitfield<3, 0> rm;
107
108 Bitfield<11, 8> rs;
109
110 SubBitUnion(puswl, 24, 20)
111 Bitfield<24> prepost;
112 Bitfield<23> up;
113 Bitfield<22> psruser;
114 Bitfield<21> writeback;
115 Bitfield<20> loadOp;
116 EndSubBitUnion(puswl)
117
118 Bitfield<24, 20> pubwl;
119
120 Bitfield<7, 0> imm;
121
122 Bitfield<11, 8> rotate;
123
124 Bitfield<11, 0> immed11_0;
125 Bitfield<7, 0> immed7_0;
126
127 Bitfield<11, 8> immedHi11_8;
128 Bitfield<3, 0> immedLo3_0;
129
130 Bitfield<15, 0> regList;
131
132 Bitfield<23, 0> offset;
133
134 Bitfield<23, 0> immed23_0;
135
136 Bitfield<11, 8> cpNum;
137 Bitfield<18, 16> fn;
138 Bitfield<14, 12> fd;
139 Bitfield<3> fpRegImm;
140 Bitfield<3, 0> fm;
141 Bitfield<2, 0> fpImm;
142 Bitfield<24, 20> punwl;
143
|
145
146 // 16 bit thumb bitfields
147 Bitfield<15, 13> topcode15_13;
148 Bitfield<13, 11> topcode13_11;
149 Bitfield<12, 11> topcode12_11;
150 Bitfield<12, 10> topcode12_10;
151 Bitfield<11, 9> topcode11_9;
152 Bitfield<11, 8> topcode11_8;
153 Bitfield<10, 9> topcode10_9;
154 Bitfield<10, 8> topcode10_8;
155 Bitfield<9, 6> topcode9_6;
156 Bitfield<7> topcode7;
157 Bitfield<7, 6> topcode7_6;
158 Bitfield<7, 5> topcode7_5;
159 Bitfield<7, 4> topcode7_4;
160 Bitfield<3, 0> topcode3_0;
161
162 // 32 bit thumb bitfields
163 Bitfield<28, 27> htopcode12_11;
164 Bitfield<26, 25> htopcode10_9;
165 Bitfield<25> htopcode9;
166 Bitfield<25, 24> htopcode9_8;
167 Bitfield<25, 21> htopcode9_5;
168 Bitfield<25, 20> htopcode9_4;
169 Bitfield<24> htopcode8;
170 Bitfield<24, 23> htopcode8_7;
171 Bitfield<24, 22> htopcode8_6;
172 Bitfield<24, 21> htopcode8_5;
173 Bitfield<23> htopcode7;
174 Bitfield<23, 21> htopcode7_5;
175 Bitfield<22> htopcode6;
176 Bitfield<22, 21> htopcode6_5;
177 Bitfield<21, 20> htopcode5_4;
178 Bitfield<20> htopcode4;
179
180 Bitfield<19, 16> htrn;
181 Bitfield<20> hts;
182
183 Bitfield<15> ltopcode15;
184 Bitfield<11, 8> ltopcode11_8;
185 Bitfield<7, 6> ltopcode7_6;
186 Bitfield<7, 4> ltopcode7_4;
187 Bitfield<4> ltopcode4;
188
189 Bitfield<11, 8> ltrd;
190 Bitfield<11, 8> ltcoproc;
191 EndBitUnion(ExtMachInst)
192
193 class PCState : public GenericISA::UPCState<MachInst>
194 {
195 protected:
196
197 typedef GenericISA::UPCState<MachInst> Base;
198
199 enum FlagBits {
200 ThumbBit = (1 << 0),
201 JazelleBit = (1 << 1)
202 };
203 uint8_t flags;
204 uint8_t nextFlags;
205
206 public:
207 PCState() : flags(0), nextFlags(0)
208 {}
209
210 void
211 set(Addr val)
212 {
213 Base::set(val);
214 npc(val + (thumb() ? 2 : 4));
215 }
216
217 PCState(Addr val) : flags(0), nextFlags(0)
218 { set(val); }
219
220 bool
221 thumb() const
222 {
223 return flags & ThumbBit;
224 }
225
226 void
227 thumb(bool val)
228 {
229 if (val)
230 flags |= ThumbBit;
231 else
232 flags &= ~ThumbBit;
233 }
234
235 bool
236 nextThumb() const
237 {
238 return nextFlags & ThumbBit;
239 }
240
241 void
242 nextThumb(bool val)
243 {
244 if (val)
245 nextFlags |= ThumbBit;
246 else
247 nextFlags &= ~ThumbBit;
248 }
249
250 bool
251 jazelle() const
252 {
253 return flags & JazelleBit;
254 }
255
256 void
257 jazelle(bool val)
258 {
259 if (val)
260 flags |= JazelleBit;
261 else
262 flags &= ~JazelleBit;
263 }
264
265 bool
266 nextJazelle() const
267 {
268 return nextFlags & JazelleBit;
269 }
270
271 void
272 nextJazelle(bool val)
273 {
274 if (val)
275 nextFlags |= JazelleBit;
276 else
277 nextFlags &= ~JazelleBit;
278 }
279
280 void
281 advance()
282 {
283 Base::advance();
284 npc(pc() + (thumb() ? 2 : 4));
285 flags = nextFlags;
286 }
287
288 void
289 uEnd()
290 {
291 advance();
292 upc(0);
293 nupc(1);
294 }
295
296 Addr
297 instPC() const
298 {
299 return pc() + (thumb() ? 4 : 8);
300 }
301
302 void
303 instNPC(uint32_t val)
304 {
305 npc(val &~ mask(nextThumb() ? 1 : 2));
306 }
307
308 Addr
309 instNPC() const
310 {
311 return npc();
312 }
313
314 // Perform an interworking branch.
315 void
316 instIWNPC(uint32_t val)
317 {
318 bool thumbEE = (thumb() && jazelle());
319
320 Addr newPC = val;
321 if (thumbEE) {
322 if (bits(newPC, 0)) {
323 newPC = newPC & ~mask(1);
324 } else {
325 panic("Bad thumbEE interworking branch address %#x.\n",
326 newPC);
327 }
328 } else {
329 if (bits(newPC, 0)) {
330 nextThumb(true);
331 newPC = newPC & ~mask(1);
332 } else if (!bits(newPC, 1)) {
333 nextThumb(false);
334 } else {
335 warn("Bad interworking branch address %#x.\n", newPC);
336 }
337 }
338 npc(newPC);
339 }
340
341 // Perform an interworking branch in ARM mode, a regular branch
342 // otherwise.
343 void
344 instAIWNPC(uint32_t val)
345 {
346 if (!thumb() && !jazelle())
347 instIWNPC(val);
348 else
349 instNPC(val);
350 }
351
352 bool
353 operator == (const PCState &opc) const
354 {
355 return Base::operator == (opc) &&
356 flags == opc.flags && nextFlags == opc.nextFlags;
357 }
358
359 void
360 serialize(std::ostream &os)
361 {
362 Base::serialize(os);
363 SERIALIZE_SCALAR(flags);
364 SERIALIZE_SCALAR(nextFlags);
365 }
366
367 void
368 unserialize(Checkpoint *cp, const std::string §ion)
369 {
370 Base::unserialize(cp, section);
371 UNSERIALIZE_SCALAR(flags);
372 UNSERIALIZE_SCALAR(nextFlags);
373 }
374 };
375
376 // Shift types for ARM instructions
377 enum ArmShiftType {
378 LSL = 0,
379 LSR,
380 ASR,
381 ROR
382 };
383
384 typedef uint64_t LargestRead;
385 // Need to use 64 bits to make sure that read requests get handled properly
386
387 typedef int RegContextParam;
388 typedef int RegContextVal;
389
390 //used in FP convert & round function
391 enum ConvertType{
392 SINGLE_TO_DOUBLE,
393 SINGLE_TO_WORD,
394 SINGLE_TO_LONG,
395
396 DOUBLE_TO_SINGLE,
397 DOUBLE_TO_WORD,
398 DOUBLE_TO_LONG,
399
400 LONG_TO_SINGLE,
401 LONG_TO_DOUBLE,
402 LONG_TO_WORD,
403 LONG_TO_PS,
404
405 WORD_TO_SINGLE,
406 WORD_TO_DOUBLE,
407 WORD_TO_LONG,
408 WORD_TO_PS,
409
410 PL_TO_SINGLE,
411 PU_TO_SINGLE
412 };
413
414 //used in FP convert & round function
415 enum RoundMode{
416 RND_ZERO,
417 RND_DOWN,
418 RND_UP,
419 RND_NEAREST
420 };
421
422 enum OperatingMode {
423 MODE_USER = 16,
424 MODE_FIQ = 17,
425 MODE_IRQ = 18,
426 MODE_SVC = 19,
427 MODE_MON = 22,
428 MODE_ABORT = 23,
429 MODE_UNDEFINED = 27,
430 MODE_SYSTEM = 31,
431 MODE_MAXMODE = MODE_SYSTEM
432 };
433
434 static inline bool
435 badMode(OperatingMode mode)
436 {
437 switch (mode) {
438 case MODE_USER:
439 case MODE_FIQ:
440 case MODE_IRQ:
441 case MODE_SVC:
442 case MODE_MON:
443 case MODE_ABORT:
444 case MODE_UNDEFINED:
445 case MODE_SYSTEM:
446 return false;
447 default:
448 return true;
449 }
450 }
451
452 struct CoreSpecific {
453 // Empty for now on the ARM
454 };
455
456} // namespace ArmISA
457
458namespace __hash_namespace {
459 template<>
460 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
461 size_t operator()(const ArmISA::ExtMachInst &emi) const {
462 return hash<uint32_t>::operator()((uint32_t)emi);
463 };
464 };
465}
466
467#endif
| 145
146 // 16 bit thumb bitfields
147 Bitfield<15, 13> topcode15_13;
148 Bitfield<13, 11> topcode13_11;
149 Bitfield<12, 11> topcode12_11;
150 Bitfield<12, 10> topcode12_10;
151 Bitfield<11, 9> topcode11_9;
152 Bitfield<11, 8> topcode11_8;
153 Bitfield<10, 9> topcode10_9;
154 Bitfield<10, 8> topcode10_8;
155 Bitfield<9, 6> topcode9_6;
156 Bitfield<7> topcode7;
157 Bitfield<7, 6> topcode7_6;
158 Bitfield<7, 5> topcode7_5;
159 Bitfield<7, 4> topcode7_4;
160 Bitfield<3, 0> topcode3_0;
161
162 // 32 bit thumb bitfields
163 Bitfield<28, 27> htopcode12_11;
164 Bitfield<26, 25> htopcode10_9;
165 Bitfield<25> htopcode9;
166 Bitfield<25, 24> htopcode9_8;
167 Bitfield<25, 21> htopcode9_5;
168 Bitfield<25, 20> htopcode9_4;
169 Bitfield<24> htopcode8;
170 Bitfield<24, 23> htopcode8_7;
171 Bitfield<24, 22> htopcode8_6;
172 Bitfield<24, 21> htopcode8_5;
173 Bitfield<23> htopcode7;
174 Bitfield<23, 21> htopcode7_5;
175 Bitfield<22> htopcode6;
176 Bitfield<22, 21> htopcode6_5;
177 Bitfield<21, 20> htopcode5_4;
178 Bitfield<20> htopcode4;
179
180 Bitfield<19, 16> htrn;
181 Bitfield<20> hts;
182
183 Bitfield<15> ltopcode15;
184 Bitfield<11, 8> ltopcode11_8;
185 Bitfield<7, 6> ltopcode7_6;
186 Bitfield<7, 4> ltopcode7_4;
187 Bitfield<4> ltopcode4;
188
189 Bitfield<11, 8> ltrd;
190 Bitfield<11, 8> ltcoproc;
191 EndBitUnion(ExtMachInst)
192
193 class PCState : public GenericISA::UPCState<MachInst>
194 {
195 protected:
196
197 typedef GenericISA::UPCState<MachInst> Base;
198
199 enum FlagBits {
200 ThumbBit = (1 << 0),
201 JazelleBit = (1 << 1)
202 };
203 uint8_t flags;
204 uint8_t nextFlags;
205
206 public:
207 PCState() : flags(0), nextFlags(0)
208 {}
209
210 void
211 set(Addr val)
212 {
213 Base::set(val);
214 npc(val + (thumb() ? 2 : 4));
215 }
216
217 PCState(Addr val) : flags(0), nextFlags(0)
218 { set(val); }
219
220 bool
221 thumb() const
222 {
223 return flags & ThumbBit;
224 }
225
226 void
227 thumb(bool val)
228 {
229 if (val)
230 flags |= ThumbBit;
231 else
232 flags &= ~ThumbBit;
233 }
234
235 bool
236 nextThumb() const
237 {
238 return nextFlags & ThumbBit;
239 }
240
241 void
242 nextThumb(bool val)
243 {
244 if (val)
245 nextFlags |= ThumbBit;
246 else
247 nextFlags &= ~ThumbBit;
248 }
249
250 bool
251 jazelle() const
252 {
253 return flags & JazelleBit;
254 }
255
256 void
257 jazelle(bool val)
258 {
259 if (val)
260 flags |= JazelleBit;
261 else
262 flags &= ~JazelleBit;
263 }
264
265 bool
266 nextJazelle() const
267 {
268 return nextFlags & JazelleBit;
269 }
270
271 void
272 nextJazelle(bool val)
273 {
274 if (val)
275 nextFlags |= JazelleBit;
276 else
277 nextFlags &= ~JazelleBit;
278 }
279
280 void
281 advance()
282 {
283 Base::advance();
284 npc(pc() + (thumb() ? 2 : 4));
285 flags = nextFlags;
286 }
287
288 void
289 uEnd()
290 {
291 advance();
292 upc(0);
293 nupc(1);
294 }
295
296 Addr
297 instPC() const
298 {
299 return pc() + (thumb() ? 4 : 8);
300 }
301
302 void
303 instNPC(uint32_t val)
304 {
305 npc(val &~ mask(nextThumb() ? 1 : 2));
306 }
307
308 Addr
309 instNPC() const
310 {
311 return npc();
312 }
313
314 // Perform an interworking branch.
315 void
316 instIWNPC(uint32_t val)
317 {
318 bool thumbEE = (thumb() && jazelle());
319
320 Addr newPC = val;
321 if (thumbEE) {
322 if (bits(newPC, 0)) {
323 newPC = newPC & ~mask(1);
324 } else {
325 panic("Bad thumbEE interworking branch address %#x.\n",
326 newPC);
327 }
328 } else {
329 if (bits(newPC, 0)) {
330 nextThumb(true);
331 newPC = newPC & ~mask(1);
332 } else if (!bits(newPC, 1)) {
333 nextThumb(false);
334 } else {
335 warn("Bad interworking branch address %#x.\n", newPC);
336 }
337 }
338 npc(newPC);
339 }
340
341 // Perform an interworking branch in ARM mode, a regular branch
342 // otherwise.
343 void
344 instAIWNPC(uint32_t val)
345 {
346 if (!thumb() && !jazelle())
347 instIWNPC(val);
348 else
349 instNPC(val);
350 }
351
352 bool
353 operator == (const PCState &opc) const
354 {
355 return Base::operator == (opc) &&
356 flags == opc.flags && nextFlags == opc.nextFlags;
357 }
358
359 void
360 serialize(std::ostream &os)
361 {
362 Base::serialize(os);
363 SERIALIZE_SCALAR(flags);
364 SERIALIZE_SCALAR(nextFlags);
365 }
366
367 void
368 unserialize(Checkpoint *cp, const std::string §ion)
369 {
370 Base::unserialize(cp, section);
371 UNSERIALIZE_SCALAR(flags);
372 UNSERIALIZE_SCALAR(nextFlags);
373 }
374 };
375
376 // Shift types for ARM instructions
377 enum ArmShiftType {
378 LSL = 0,
379 LSR,
380 ASR,
381 ROR
382 };
383
384 typedef uint64_t LargestRead;
385 // Need to use 64 bits to make sure that read requests get handled properly
386
387 typedef int RegContextParam;
388 typedef int RegContextVal;
389
390 //used in FP convert & round function
391 enum ConvertType{
392 SINGLE_TO_DOUBLE,
393 SINGLE_TO_WORD,
394 SINGLE_TO_LONG,
395
396 DOUBLE_TO_SINGLE,
397 DOUBLE_TO_WORD,
398 DOUBLE_TO_LONG,
399
400 LONG_TO_SINGLE,
401 LONG_TO_DOUBLE,
402 LONG_TO_WORD,
403 LONG_TO_PS,
404
405 WORD_TO_SINGLE,
406 WORD_TO_DOUBLE,
407 WORD_TO_LONG,
408 WORD_TO_PS,
409
410 PL_TO_SINGLE,
411 PU_TO_SINGLE
412 };
413
414 //used in FP convert & round function
415 enum RoundMode{
416 RND_ZERO,
417 RND_DOWN,
418 RND_UP,
419 RND_NEAREST
420 };
421
422 enum OperatingMode {
423 MODE_USER = 16,
424 MODE_FIQ = 17,
425 MODE_IRQ = 18,
426 MODE_SVC = 19,
427 MODE_MON = 22,
428 MODE_ABORT = 23,
429 MODE_UNDEFINED = 27,
430 MODE_SYSTEM = 31,
431 MODE_MAXMODE = MODE_SYSTEM
432 };
433
434 static inline bool
435 badMode(OperatingMode mode)
436 {
437 switch (mode) {
438 case MODE_USER:
439 case MODE_FIQ:
440 case MODE_IRQ:
441 case MODE_SVC:
442 case MODE_MON:
443 case MODE_ABORT:
444 case MODE_UNDEFINED:
445 case MODE_SYSTEM:
446 return false;
447 default:
448 return true;
449 }
450 }
451
452 struct CoreSpecific {
453 // Empty for now on the ARM
454 };
455
456} // namespace ArmISA
457
458namespace __hash_namespace {
459 template<>
460 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
461 size_t operator()(const ArmISA::ExtMachInst &emi) const {
462 return hash<uint32_t>::operator()((uint32_t)emi);
463 };
464 };
465}
466
467#endif
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