1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_TYPES_HH__ 44#define __ARCH_ARM_TYPES_HH__ 45 46#include "base/bitunion.hh" 47#include "base/types.hh" 48 49namespace ArmISA 50{ 51 typedef uint32_t MachInst; 52 53 BitUnion64(ExtMachInst)
| 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_TYPES_HH__ 44#define __ARCH_ARM_TYPES_HH__ 45 46#include "base/bitunion.hh" 47#include "base/types.hh" 48 49namespace ArmISA 50{ 51 typedef uint32_t MachInst; 52 53 BitUnion64(ExtMachInst)
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54 // FPSCR fields 55 Bitfield<41, 40> fpscrStride; 56 Bitfield<39, 37> fpscrLen; 57 58 // Bitfields to select mode. 59 Bitfield<36> thumb; 60 Bitfield<35> bigThumb; 61 62 // Made up bitfields that make life easier. 63 Bitfield<33> sevenAndFour; 64 Bitfield<32> isMisc; 65 66 uint32_t instBits; 67 68 // All the different types of opcode fields. 69 Bitfield<27, 25> encoding; 70 Bitfield<25> useImm; 71 Bitfield<24, 21> opcode; 72 Bitfield<24, 20> mediaOpcode; 73 Bitfield<24> opcode24; 74 Bitfield<24, 23> opcode24_23; 75 Bitfield<23, 20> opcode23_20; 76 Bitfield<23, 21> opcode23_21; 77 Bitfield<20> opcode20; 78 Bitfield<22> opcode22; 79 Bitfield<19, 16> opcode19_16; 80 Bitfield<19> opcode19; 81 Bitfield<18> opcode18; 82 Bitfield<15, 12> opcode15_12; 83 Bitfield<15> opcode15; 84 Bitfield<7, 4> miscOpcode; 85 Bitfield<7,5> opc2; 86 Bitfield<7> opcode7; 87 Bitfield<6> opcode6; 88 Bitfield<4> opcode4; 89 90 Bitfield<31, 28> condCode; 91 Bitfield<20> sField; 92 Bitfield<19, 16> rn; 93 Bitfield<15, 12> rd; 94 Bitfield<15, 12> rt; 95 Bitfield<11, 7> shiftSize; 96 Bitfield<6, 5> shift; 97 Bitfield<3, 0> rm; 98 99 Bitfield<11, 8> rs; 100 101 SubBitUnion(puswl, 24, 20) 102 Bitfield<24> prepost; 103 Bitfield<23> up; 104 Bitfield<22> psruser; 105 Bitfield<21> writeback; 106 Bitfield<20> loadOp; 107 EndSubBitUnion(puswl) 108 109 Bitfield<24, 20> pubwl; 110 111 Bitfield<7, 0> imm; 112 113 Bitfield<11, 8> rotate; 114 115 Bitfield<11, 0> immed11_0; 116 Bitfield<7, 0> immed7_0; 117 118 Bitfield<11, 8> immedHi11_8; 119 Bitfield<3, 0> immedLo3_0; 120 121 Bitfield<15, 0> regList; 122 123 Bitfield<23, 0> offset; 124 125 Bitfield<23, 0> immed23_0; 126 127 Bitfield<11, 8> cpNum; 128 Bitfield<18, 16> fn; 129 Bitfield<14, 12> fd; 130 Bitfield<3> fpRegImm; 131 Bitfield<3, 0> fm; 132 Bitfield<2, 0> fpImm; 133 Bitfield<24, 20> punwl; 134 135 Bitfield<7, 0> m5Func; 136 137 // 16 bit thumb bitfields 138 Bitfield<15, 13> topcode15_13; 139 Bitfield<13, 11> topcode13_11; 140 Bitfield<12, 11> topcode12_11; 141 Bitfield<12, 10> topcode12_10; 142 Bitfield<11, 9> topcode11_9; 143 Bitfield<11, 8> topcode11_8; 144 Bitfield<10, 9> topcode10_9; 145 Bitfield<10, 8> topcode10_8; 146 Bitfield<9, 6> topcode9_6; 147 Bitfield<7> topcode7; 148 Bitfield<7, 6> topcode7_6; 149 Bitfield<7, 5> topcode7_5; 150 Bitfield<7, 4> topcode7_4; 151 Bitfield<3, 0> topcode3_0; 152 153 // 32 bit thumb bitfields 154 Bitfield<28, 27> htopcode12_11; 155 Bitfield<26, 25> htopcode10_9; 156 Bitfield<25> htopcode9; 157 Bitfield<25, 24> htopcode9_8; 158 Bitfield<25, 21> htopcode9_5; 159 Bitfield<25, 20> htopcode9_4; 160 Bitfield<24> htopcode8; 161 Bitfield<24, 23> htopcode8_7; 162 Bitfield<24, 22> htopcode8_6; 163 Bitfield<24, 21> htopcode8_5; 164 Bitfield<23> htopcode7; 165 Bitfield<23, 21> htopcode7_5; 166 Bitfield<22> htopcode6; 167 Bitfield<22, 21> htopcode6_5; 168 Bitfield<21, 20> htopcode5_4; 169 Bitfield<20> htopcode4; 170 171 Bitfield<19, 16> htrn; 172 Bitfield<20> hts; 173 174 Bitfield<15> ltopcode15; 175 Bitfield<11, 8> ltopcode11_8; 176 Bitfield<7, 6> ltopcode7_6; 177 Bitfield<7, 4> ltopcode7_4; 178 Bitfield<4> ltopcode4; 179 180 Bitfield<11, 8> ltrd; 181 Bitfield<11, 8> ltcoproc; 182 EndBitUnion(ExtMachInst) 183 184 // Shift types for ARM instructions 185 enum ArmShiftType { 186 LSL = 0, 187 LSR, 188 ASR, 189 ROR 190 }; 191 192 typedef uint64_t LargestRead; 193 // Need to use 64 bits to make sure that read requests get handled properly 194 195 typedef int RegContextParam; 196 typedef int RegContextVal; 197 198 //used in FP convert & round function 199 enum ConvertType{ 200 SINGLE_TO_DOUBLE, 201 SINGLE_TO_WORD, 202 SINGLE_TO_LONG, 203 204 DOUBLE_TO_SINGLE, 205 DOUBLE_TO_WORD, 206 DOUBLE_TO_LONG, 207 208 LONG_TO_SINGLE, 209 LONG_TO_DOUBLE, 210 LONG_TO_WORD, 211 LONG_TO_PS, 212 213 WORD_TO_SINGLE, 214 WORD_TO_DOUBLE, 215 WORD_TO_LONG, 216 WORD_TO_PS, 217 218 PL_TO_SINGLE, 219 PU_TO_SINGLE 220 }; 221 222 //used in FP convert & round function 223 enum RoundMode{ 224 RND_ZERO, 225 RND_DOWN, 226 RND_UP, 227 RND_NEAREST 228 }; 229 230 enum OperatingMode { 231 MODE_USER = 16, 232 MODE_FIQ = 17, 233 MODE_IRQ = 18, 234 MODE_SVC = 19, 235 MODE_MON = 22, 236 MODE_ABORT = 23, 237 MODE_UNDEFINED = 27, 238 MODE_SYSTEM = 31 239 }; 240 241 static inline bool 242 badMode(OperatingMode mode) 243 { 244 switch (mode) { 245 case MODE_USER: 246 case MODE_FIQ: 247 case MODE_IRQ: 248 case MODE_SVC: 249 case MODE_MON: 250 case MODE_ABORT: 251 case MODE_UNDEFINED: 252 case MODE_SYSTEM: 253 return false; 254 default: 255 return true; 256 } 257 } 258 259 struct CoreSpecific { 260 // Empty for now on the ARM 261 }; 262 263} // namespace ArmISA 264 265#endif
| 60 // FPSCR fields 61 Bitfield<41, 40> fpscrStride; 62 Bitfield<39, 37> fpscrLen; 63 64 // Bitfields to select mode. 65 Bitfield<36> thumb; 66 Bitfield<35> bigThumb; 67 68 // Made up bitfields that make life easier. 69 Bitfield<33> sevenAndFour; 70 Bitfield<32> isMisc; 71 72 uint32_t instBits; 73 74 // All the different types of opcode fields. 75 Bitfield<27, 25> encoding; 76 Bitfield<25> useImm; 77 Bitfield<24, 21> opcode; 78 Bitfield<24, 20> mediaOpcode; 79 Bitfield<24> opcode24; 80 Bitfield<24, 23> opcode24_23; 81 Bitfield<23, 20> opcode23_20; 82 Bitfield<23, 21> opcode23_21; 83 Bitfield<20> opcode20; 84 Bitfield<22> opcode22; 85 Bitfield<19, 16> opcode19_16; 86 Bitfield<19> opcode19; 87 Bitfield<18> opcode18; 88 Bitfield<15, 12> opcode15_12; 89 Bitfield<15> opcode15; 90 Bitfield<7, 4> miscOpcode; 91 Bitfield<7,5> opc2; 92 Bitfield<7> opcode7; 93 Bitfield<6> opcode6; 94 Bitfield<4> opcode4; 95 96 Bitfield<31, 28> condCode; 97 Bitfield<20> sField; 98 Bitfield<19, 16> rn; 99 Bitfield<15, 12> rd; 100 Bitfield<15, 12> rt; 101 Bitfield<11, 7> shiftSize; 102 Bitfield<6, 5> shift; 103 Bitfield<3, 0> rm; 104 105 Bitfield<11, 8> rs; 106 107 SubBitUnion(puswl, 24, 20) 108 Bitfield<24> prepost; 109 Bitfield<23> up; 110 Bitfield<22> psruser; 111 Bitfield<21> writeback; 112 Bitfield<20> loadOp; 113 EndSubBitUnion(puswl) 114 115 Bitfield<24, 20> pubwl; 116 117 Bitfield<7, 0> imm; 118 119 Bitfield<11, 8> rotate; 120 121 Bitfield<11, 0> immed11_0; 122 Bitfield<7, 0> immed7_0; 123 124 Bitfield<11, 8> immedHi11_8; 125 Bitfield<3, 0> immedLo3_0; 126 127 Bitfield<15, 0> regList; 128 129 Bitfield<23, 0> offset; 130 131 Bitfield<23, 0> immed23_0; 132 133 Bitfield<11, 8> cpNum; 134 Bitfield<18, 16> fn; 135 Bitfield<14, 12> fd; 136 Bitfield<3> fpRegImm; 137 Bitfield<3, 0> fm; 138 Bitfield<2, 0> fpImm; 139 Bitfield<24, 20> punwl; 140 141 Bitfield<7, 0> m5Func; 142 143 // 16 bit thumb bitfields 144 Bitfield<15, 13> topcode15_13; 145 Bitfield<13, 11> topcode13_11; 146 Bitfield<12, 11> topcode12_11; 147 Bitfield<12, 10> topcode12_10; 148 Bitfield<11, 9> topcode11_9; 149 Bitfield<11, 8> topcode11_8; 150 Bitfield<10, 9> topcode10_9; 151 Bitfield<10, 8> topcode10_8; 152 Bitfield<9, 6> topcode9_6; 153 Bitfield<7> topcode7; 154 Bitfield<7, 6> topcode7_6; 155 Bitfield<7, 5> topcode7_5; 156 Bitfield<7, 4> topcode7_4; 157 Bitfield<3, 0> topcode3_0; 158 159 // 32 bit thumb bitfields 160 Bitfield<28, 27> htopcode12_11; 161 Bitfield<26, 25> htopcode10_9; 162 Bitfield<25> htopcode9; 163 Bitfield<25, 24> htopcode9_8; 164 Bitfield<25, 21> htopcode9_5; 165 Bitfield<25, 20> htopcode9_4; 166 Bitfield<24> htopcode8; 167 Bitfield<24, 23> htopcode8_7; 168 Bitfield<24, 22> htopcode8_6; 169 Bitfield<24, 21> htopcode8_5; 170 Bitfield<23> htopcode7; 171 Bitfield<23, 21> htopcode7_5; 172 Bitfield<22> htopcode6; 173 Bitfield<22, 21> htopcode6_5; 174 Bitfield<21, 20> htopcode5_4; 175 Bitfield<20> htopcode4; 176 177 Bitfield<19, 16> htrn; 178 Bitfield<20> hts; 179 180 Bitfield<15> ltopcode15; 181 Bitfield<11, 8> ltopcode11_8; 182 Bitfield<7, 6> ltopcode7_6; 183 Bitfield<7, 4> ltopcode7_4; 184 Bitfield<4> ltopcode4; 185 186 Bitfield<11, 8> ltrd; 187 Bitfield<11, 8> ltcoproc; 188 EndBitUnion(ExtMachInst) 189 190 // Shift types for ARM instructions 191 enum ArmShiftType { 192 LSL = 0, 193 LSR, 194 ASR, 195 ROR 196 }; 197 198 typedef uint64_t LargestRead; 199 // Need to use 64 bits to make sure that read requests get handled properly 200 201 typedef int RegContextParam; 202 typedef int RegContextVal; 203 204 //used in FP convert & round function 205 enum ConvertType{ 206 SINGLE_TO_DOUBLE, 207 SINGLE_TO_WORD, 208 SINGLE_TO_LONG, 209 210 DOUBLE_TO_SINGLE, 211 DOUBLE_TO_WORD, 212 DOUBLE_TO_LONG, 213 214 LONG_TO_SINGLE, 215 LONG_TO_DOUBLE, 216 LONG_TO_WORD, 217 LONG_TO_PS, 218 219 WORD_TO_SINGLE, 220 WORD_TO_DOUBLE, 221 WORD_TO_LONG, 222 WORD_TO_PS, 223 224 PL_TO_SINGLE, 225 PU_TO_SINGLE 226 }; 227 228 //used in FP convert & round function 229 enum RoundMode{ 230 RND_ZERO, 231 RND_DOWN, 232 RND_UP, 233 RND_NEAREST 234 }; 235 236 enum OperatingMode { 237 MODE_USER = 16, 238 MODE_FIQ = 17, 239 MODE_IRQ = 18, 240 MODE_SVC = 19, 241 MODE_MON = 22, 242 MODE_ABORT = 23, 243 MODE_UNDEFINED = 27, 244 MODE_SYSTEM = 31 245 }; 246 247 static inline bool 248 badMode(OperatingMode mode) 249 { 250 switch (mode) { 251 case MODE_USER: 252 case MODE_FIQ: 253 case MODE_IRQ: 254 case MODE_SVC: 255 case MODE_MON: 256 case MODE_ABORT: 257 case MODE_UNDEFINED: 258 case MODE_SYSTEM: 259 return false; 260 default: 261 return true; 262 } 263 } 264 265 struct CoreSpecific { 266 // Empty for now on the ARM 267 }; 268 269} // namespace ArmISA 270 271#endif
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