1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_TYPES_HH__ 44#define __ARCH_ARM_TYPES_HH__ 45 46#include "base/bitunion.hh" 47#include "base/types.hh" 48 49namespace ArmISA 50{ 51 typedef uint32_t MachInst; 52 53 BitUnion64(ExtMachInst) 54 // Bitfields to select mode. 55 Bitfield<36> thumb; 56 Bitfield<35> bigThumb; 57 58 // Made up bitfields that make life easier. 59 Bitfield<33> sevenAndFour; 60 Bitfield<32> isMisc; 61 62 uint32_t instBits; 63 64 // All the different types of opcode fields. 65 Bitfield<27, 25> encoding; 66 Bitfield<25> useImm; 67 Bitfield<24, 21> opcode; 68 Bitfield<24, 20> mediaOpcode; 69 Bitfield<24> opcode24; 70 Bitfield<23, 20> opcode23_20; 71 Bitfield<23, 21> opcode23_21; 72 Bitfield<20> opcode20; 73 Bitfield<22> opcode22; 74 Bitfield<19, 16> opcode19_16; 75 Bitfield<19> opcode19; 76 Bitfield<18> opcode18; 77 Bitfield<15, 12> opcode15_12; 78 Bitfield<15> opcode15; 79 Bitfield<7, 4> miscOpcode; 80 Bitfield<7,5> opc2; 81 Bitfield<7> opcode7; 82 Bitfield<6> opcode6; 83 Bitfield<4> opcode4; 84 85 Bitfield<31, 28> condCode; 86 Bitfield<20> sField; 87 Bitfield<19, 16> rn; 88 Bitfield<15, 12> rd; 89 Bitfield<11, 7> shiftSize; 90 Bitfield<6, 5> shift; 91 Bitfield<3, 0> rm; 92 93 Bitfield<11, 8> rs; 94 95 SubBitUnion(puswl, 24, 20) 96 Bitfield<24> prepost; 97 Bitfield<23> up; 98 Bitfield<22> psruser; 99 Bitfield<21> writeback; 100 Bitfield<20> loadOp; 101 EndSubBitUnion(puswl) 102 103 Bitfield<24, 20> pubwl; 104 105 Bitfield<7, 0> imm; 106 107 Bitfield<11, 8> rotate; 108 109 Bitfield<11, 0> immed11_0; 110 Bitfield<7, 0> immed7_0; 111 112 Bitfield<11, 8> immedHi11_8; 113 Bitfield<3, 0> immedLo3_0; 114 115 Bitfield<15, 0> regList; 116 117 Bitfield<23, 0> offset; 118 119 Bitfield<23, 0> immed23_0; 120 121 Bitfield<11, 8> cpNum; 122 Bitfield<18, 16> fn; 123 Bitfield<14, 12> fd; 124 Bitfield<3> fpRegImm; 125 Bitfield<3, 0> fm; 126 Bitfield<2, 0> fpImm; 127 Bitfield<24, 20> punwl; 128 129 Bitfield<7, 0> m5Func; 130 131 // 16 bit thumb bitfields 132 Bitfield<15, 13> topcode15_13; 133 Bitfield<13, 11> topcode13_11; 134 Bitfield<12, 11> topcode12_11; 135 Bitfield<12, 10> topcode12_10; 136 Bitfield<11, 9> topcode11_9; 137 Bitfield<11, 8> topcode11_8; 138 Bitfield<10, 9> topcode10_9; 139 Bitfield<10, 8> topcode10_8; 140 Bitfield<9, 6> topcode9_6; 141 Bitfield<7> topcode7; 142 Bitfield<7, 6> topcode7_6; 143 Bitfield<7, 5> topcode7_5; 144 Bitfield<7, 4> topcode7_4; 145 Bitfield<3, 0> topcode3_0; 146 147 // 32 bit thumb bitfields 148 Bitfield<28, 27> htopcode12_11; 149 Bitfield<26, 25> htopcode10_9; 150 Bitfield<25> htopcode9; 151 Bitfield<25, 24> htopcode9_8; 152 Bitfield<25, 21> htopcode9_5; 153 Bitfield<25, 20> htopcode9_4; 154 Bitfield<24> htopcode8; 155 Bitfield<24, 23> htopcode8_7; 156 Bitfield<24, 22> htopcode8_6; 157 Bitfield<24, 21> htopcode8_5; 158 Bitfield<23> htopcode7;
| 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_TYPES_HH__ 44#define __ARCH_ARM_TYPES_HH__ 45 46#include "base/bitunion.hh" 47#include "base/types.hh" 48 49namespace ArmISA 50{ 51 typedef uint32_t MachInst; 52 53 BitUnion64(ExtMachInst) 54 // Bitfields to select mode. 55 Bitfield<36> thumb; 56 Bitfield<35> bigThumb; 57 58 // Made up bitfields that make life easier. 59 Bitfield<33> sevenAndFour; 60 Bitfield<32> isMisc; 61 62 uint32_t instBits; 63 64 // All the different types of opcode fields. 65 Bitfield<27, 25> encoding; 66 Bitfield<25> useImm; 67 Bitfield<24, 21> opcode; 68 Bitfield<24, 20> mediaOpcode; 69 Bitfield<24> opcode24; 70 Bitfield<23, 20> opcode23_20; 71 Bitfield<23, 21> opcode23_21; 72 Bitfield<20> opcode20; 73 Bitfield<22> opcode22; 74 Bitfield<19, 16> opcode19_16; 75 Bitfield<19> opcode19; 76 Bitfield<18> opcode18; 77 Bitfield<15, 12> opcode15_12; 78 Bitfield<15> opcode15; 79 Bitfield<7, 4> miscOpcode; 80 Bitfield<7,5> opc2; 81 Bitfield<7> opcode7; 82 Bitfield<6> opcode6; 83 Bitfield<4> opcode4; 84 85 Bitfield<31, 28> condCode; 86 Bitfield<20> sField; 87 Bitfield<19, 16> rn; 88 Bitfield<15, 12> rd; 89 Bitfield<11, 7> shiftSize; 90 Bitfield<6, 5> shift; 91 Bitfield<3, 0> rm; 92 93 Bitfield<11, 8> rs; 94 95 SubBitUnion(puswl, 24, 20) 96 Bitfield<24> prepost; 97 Bitfield<23> up; 98 Bitfield<22> psruser; 99 Bitfield<21> writeback; 100 Bitfield<20> loadOp; 101 EndSubBitUnion(puswl) 102 103 Bitfield<24, 20> pubwl; 104 105 Bitfield<7, 0> imm; 106 107 Bitfield<11, 8> rotate; 108 109 Bitfield<11, 0> immed11_0; 110 Bitfield<7, 0> immed7_0; 111 112 Bitfield<11, 8> immedHi11_8; 113 Bitfield<3, 0> immedLo3_0; 114 115 Bitfield<15, 0> regList; 116 117 Bitfield<23, 0> offset; 118 119 Bitfield<23, 0> immed23_0; 120 121 Bitfield<11, 8> cpNum; 122 Bitfield<18, 16> fn; 123 Bitfield<14, 12> fd; 124 Bitfield<3> fpRegImm; 125 Bitfield<3, 0> fm; 126 Bitfield<2, 0> fpImm; 127 Bitfield<24, 20> punwl; 128 129 Bitfield<7, 0> m5Func; 130 131 // 16 bit thumb bitfields 132 Bitfield<15, 13> topcode15_13; 133 Bitfield<13, 11> topcode13_11; 134 Bitfield<12, 11> topcode12_11; 135 Bitfield<12, 10> topcode12_10; 136 Bitfield<11, 9> topcode11_9; 137 Bitfield<11, 8> topcode11_8; 138 Bitfield<10, 9> topcode10_9; 139 Bitfield<10, 8> topcode10_8; 140 Bitfield<9, 6> topcode9_6; 141 Bitfield<7> topcode7; 142 Bitfield<7, 6> topcode7_6; 143 Bitfield<7, 5> topcode7_5; 144 Bitfield<7, 4> topcode7_4; 145 Bitfield<3, 0> topcode3_0; 146 147 // 32 bit thumb bitfields 148 Bitfield<28, 27> htopcode12_11; 149 Bitfield<26, 25> htopcode10_9; 150 Bitfield<25> htopcode9; 151 Bitfield<25, 24> htopcode9_8; 152 Bitfield<25, 21> htopcode9_5; 153 Bitfield<25, 20> htopcode9_4; 154 Bitfield<24> htopcode8; 155 Bitfield<24, 23> htopcode8_7; 156 Bitfield<24, 22> htopcode8_6; 157 Bitfield<24, 21> htopcode8_5; 158 Bitfield<23> htopcode7;
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159 Bitfield<22, 21> htopcode6_5; 160 Bitfield<21, 20> htopcode5_4; 161 Bitfield<20> htopcode4; 162 163 Bitfield<19, 16> htrn; 164 Bitfield<20> hts; 165 166 Bitfield<15> ltopcode15; 167 Bitfield<11, 8> ltopcode11_8; 168 Bitfield<7, 6> ltopcode7_6; 169 Bitfield<7, 4> ltopcode7_4; 170 Bitfield<4> ltopcode4; 171 172 Bitfield<11, 8> ltrd; 173 Bitfield<11, 8> ltcoproc; 174 EndBitUnion(ExtMachInst) 175 176 // Shift types for ARM instructions 177 enum ArmShiftType { 178 LSL = 0, 179 LSR, 180 ASR, 181 ROR 182 }; 183 184 typedef uint64_t LargestRead; 185 // Need to use 64 bits to make sure that read requests get handled properly 186 187 typedef int RegContextParam; 188 typedef int RegContextVal; 189 190 //used in FP convert & round function 191 enum ConvertType{ 192 SINGLE_TO_DOUBLE, 193 SINGLE_TO_WORD, 194 SINGLE_TO_LONG, 195 196 DOUBLE_TO_SINGLE, 197 DOUBLE_TO_WORD, 198 DOUBLE_TO_LONG, 199 200 LONG_TO_SINGLE, 201 LONG_TO_DOUBLE, 202 LONG_TO_WORD, 203 LONG_TO_PS, 204 205 WORD_TO_SINGLE, 206 WORD_TO_DOUBLE, 207 WORD_TO_LONG, 208 WORD_TO_PS, 209 210 PL_TO_SINGLE, 211 PU_TO_SINGLE 212 }; 213 214 //used in FP convert & round function 215 enum RoundMode{ 216 RND_ZERO, 217 RND_DOWN, 218 RND_UP, 219 RND_NEAREST 220 }; 221 222 enum OperatingMode { 223 MODE_USER = 16, 224 MODE_FIQ = 17, 225 MODE_IRQ = 18, 226 MODE_SVC = 19, 227 MODE_MON = 22, 228 MODE_ABORT = 23, 229 MODE_UNDEFINED = 27, 230 MODE_SYSTEM = 31 231 }; 232 233 struct CoreSpecific { 234 // Empty for now on the ARM 235 }; 236 237} // namespace ArmISA 238 239#endif
| 160 Bitfield<22, 21> htopcode6_5; 161 Bitfield<21, 20> htopcode5_4; 162 Bitfield<20> htopcode4; 163 164 Bitfield<19, 16> htrn; 165 Bitfield<20> hts; 166 167 Bitfield<15> ltopcode15; 168 Bitfield<11, 8> ltopcode11_8; 169 Bitfield<7, 6> ltopcode7_6; 170 Bitfield<7, 4> ltopcode7_4; 171 Bitfield<4> ltopcode4; 172 173 Bitfield<11, 8> ltrd; 174 Bitfield<11, 8> ltcoproc; 175 EndBitUnion(ExtMachInst) 176 177 // Shift types for ARM instructions 178 enum ArmShiftType { 179 LSL = 0, 180 LSR, 181 ASR, 182 ROR 183 }; 184 185 typedef uint64_t LargestRead; 186 // Need to use 64 bits to make sure that read requests get handled properly 187 188 typedef int RegContextParam; 189 typedef int RegContextVal; 190 191 //used in FP convert & round function 192 enum ConvertType{ 193 SINGLE_TO_DOUBLE, 194 SINGLE_TO_WORD, 195 SINGLE_TO_LONG, 196 197 DOUBLE_TO_SINGLE, 198 DOUBLE_TO_WORD, 199 DOUBLE_TO_LONG, 200 201 LONG_TO_SINGLE, 202 LONG_TO_DOUBLE, 203 LONG_TO_WORD, 204 LONG_TO_PS, 205 206 WORD_TO_SINGLE, 207 WORD_TO_DOUBLE, 208 WORD_TO_LONG, 209 WORD_TO_PS, 210 211 PL_TO_SINGLE, 212 PU_TO_SINGLE 213 }; 214 215 //used in FP convert & round function 216 enum RoundMode{ 217 RND_ZERO, 218 RND_DOWN, 219 RND_UP, 220 RND_NEAREST 221 }; 222 223 enum OperatingMode { 224 MODE_USER = 16, 225 MODE_FIQ = 17, 226 MODE_IRQ = 18, 227 MODE_SVC = 19, 228 MODE_MON = 22, 229 MODE_ABORT = 23, 230 MODE_UNDEFINED = 27, 231 MODE_SYSTEM = 31 232 }; 233 234 struct CoreSpecific { 235 // Empty for now on the ARM 236 }; 237 238} // namespace ArmISA 239 240#endif
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