1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Stephen Hines
29 */
30
31#ifndef __ARCH_ARM_TYPES_HH__
32#define __ARCH_ARM_TYPES_HH__
33
34#include "base/bitunion.hh"
35#include "base/types.hh"
36
37namespace ArmISA
38{
39 typedef uint32_t MachInst;
40
41 BitUnion64(ExtMachInst)
42 // Made up bitfields that make life easier.
43 Bitfield<33> sevenAndFour;
44 Bitfield<32> isMisc;
45
46 // All the different types of opcode fields.
47 Bitfield<27, 25> encoding;
| 1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Stephen Hines
29 */
30
31#ifndef __ARCH_ARM_TYPES_HH__
32#define __ARCH_ARM_TYPES_HH__
33
34#include "base/bitunion.hh"
35#include "base/types.hh"
36
37namespace ArmISA
38{
39 typedef uint32_t MachInst;
40
41 BitUnion64(ExtMachInst)
42 // Made up bitfields that make life easier.
43 Bitfield<33> sevenAndFour;
44 Bitfield<32> isMisc;
45
46 // All the different types of opcode fields.
47 Bitfield<27, 25> encoding;
|
48 Bitfield<24, 21> opcode;
49 Bitfield<24, 20> mediaOpcode;
50 Bitfield<24> opcode24;
51 Bitfield<23, 20> opcode23_20;
52 Bitfield<23, 21> opcode23_21;
53 Bitfield<20> opcode20;
54 Bitfield<22> opcode22;
55 Bitfield<19> opcode19;
56 Bitfield<18> opcode18;
57 Bitfield<15, 12> opcode15_12;
58 Bitfield<15> opcode15;
59 Bitfield<7, 4> miscOpcode;
60 Bitfield<7> opcode7;
61 Bitfield<4> opcode4;
62
63 Bitfield<31, 28> condCode;
64 Bitfield<20> sField;
65 Bitfield<19, 16> rn;
66 Bitfield<15, 12> rd;
67 Bitfield<11, 7> shiftSize;
68 Bitfield<6, 5> shift;
69 Bitfield<3, 0> rm;
70
71 Bitfield<11, 8> rs;
72
73 SubBitUnion(puswl, 24, 20)
74 Bitfield<24> prepost;
75 Bitfield<23> up;
76 Bitfield<22> psruser;
77 Bitfield<21> writeback;
78 Bitfield<20> loadOp;
79 EndSubBitUnion(puswl)
80
81 Bitfield<24, 20> pubwl;
82
83 Bitfield<7, 0> imm;
84
85 Bitfield<11, 8> rotate;
86
87 Bitfield<11, 0> immed11_0;
88 Bitfield<7, 0> immed7_0;
89
90 Bitfield<11, 8> immedHi11_8;
91 Bitfield<3, 0> immedLo3_0;
92
93 Bitfield<15, 0> regList;
94
95 Bitfield<23, 0> offset;
96
97 Bitfield<23, 0> immed23_0;
98
99 Bitfield<11, 8> cpNum;
100 Bitfield<18, 16> fn;
101 Bitfield<14, 12> fd;
102 Bitfield<3> fpRegImm;
103 Bitfield<3, 0> fm;
104 Bitfield<2, 0> fpImm;
105 Bitfield<24, 20> punwl;
106
107 Bitfield<7, 0> m5Func;
108 EndBitUnion(ExtMachInst)
109
110 // Shift types for ARM instructions
111 enum ArmShiftType {
112 LSL = 0,
113 LSR,
114 ASR,
115 ROR
116 };
117
118 typedef uint64_t LargestRead;
119 // Need to use 64 bits to make sure that read requests get handled properly
120
121 typedef int RegContextParam;
122 typedef int RegContextVal;
123
124 //used in FP convert & round function
125 enum ConvertType{
126 SINGLE_TO_DOUBLE,
127 SINGLE_TO_WORD,
128 SINGLE_TO_LONG,
129
130 DOUBLE_TO_SINGLE,
131 DOUBLE_TO_WORD,
132 DOUBLE_TO_LONG,
133
134 LONG_TO_SINGLE,
135 LONG_TO_DOUBLE,
136 LONG_TO_WORD,
137 LONG_TO_PS,
138
139 WORD_TO_SINGLE,
140 WORD_TO_DOUBLE,
141 WORD_TO_LONG,
142 WORD_TO_PS,
143
144 PL_TO_SINGLE,
145 PU_TO_SINGLE
146 };
147
148 //used in FP convert & round function
149 enum RoundMode{
150 RND_ZERO,
151 RND_DOWN,
152 RND_UP,
153 RND_NEAREST
154 };
155
156 enum OperatingMode {
157 MODE_USER = 16,
158 MODE_FIQ = 17,
159 MODE_IRQ = 18,
160 MODE_SVC = 19,
161 MODE_MON = 22,
162 MODE_ABORT = 23,
163 MODE_UNDEFINED = 27,
164 MODE_SYSTEM = 31
165 };
166
167 struct CoreSpecific {
168 // Empty for now on the ARM
169 };
170
171} // namespace ArmISA
172
173#endif
| 49 Bitfield<24, 21> opcode;
50 Bitfield<24, 20> mediaOpcode;
51 Bitfield<24> opcode24;
52 Bitfield<23, 20> opcode23_20;
53 Bitfield<23, 21> opcode23_21;
54 Bitfield<20> opcode20;
55 Bitfield<22> opcode22;
56 Bitfield<19> opcode19;
57 Bitfield<18> opcode18;
58 Bitfield<15, 12> opcode15_12;
59 Bitfield<15> opcode15;
60 Bitfield<7, 4> miscOpcode;
61 Bitfield<7> opcode7;
62 Bitfield<4> opcode4;
63
64 Bitfield<31, 28> condCode;
65 Bitfield<20> sField;
66 Bitfield<19, 16> rn;
67 Bitfield<15, 12> rd;
68 Bitfield<11, 7> shiftSize;
69 Bitfield<6, 5> shift;
70 Bitfield<3, 0> rm;
71
72 Bitfield<11, 8> rs;
73
74 SubBitUnion(puswl, 24, 20)
75 Bitfield<24> prepost;
76 Bitfield<23> up;
77 Bitfield<22> psruser;
78 Bitfield<21> writeback;
79 Bitfield<20> loadOp;
80 EndSubBitUnion(puswl)
81
82 Bitfield<24, 20> pubwl;
83
84 Bitfield<7, 0> imm;
85
86 Bitfield<11, 8> rotate;
87
88 Bitfield<11, 0> immed11_0;
89 Bitfield<7, 0> immed7_0;
90
91 Bitfield<11, 8> immedHi11_8;
92 Bitfield<3, 0> immedLo3_0;
93
94 Bitfield<15, 0> regList;
95
96 Bitfield<23, 0> offset;
97
98 Bitfield<23, 0> immed23_0;
99
100 Bitfield<11, 8> cpNum;
101 Bitfield<18, 16> fn;
102 Bitfield<14, 12> fd;
103 Bitfield<3> fpRegImm;
104 Bitfield<3, 0> fm;
105 Bitfield<2, 0> fpImm;
106 Bitfield<24, 20> punwl;
107
108 Bitfield<7, 0> m5Func;
109 EndBitUnion(ExtMachInst)
110
111 // Shift types for ARM instructions
112 enum ArmShiftType {
113 LSL = 0,
114 LSR,
115 ASR,
116 ROR
117 };
118
119 typedef uint64_t LargestRead;
120 // Need to use 64 bits to make sure that read requests get handled properly
121
122 typedef int RegContextParam;
123 typedef int RegContextVal;
124
125 //used in FP convert & round function
126 enum ConvertType{
127 SINGLE_TO_DOUBLE,
128 SINGLE_TO_WORD,
129 SINGLE_TO_LONG,
130
131 DOUBLE_TO_SINGLE,
132 DOUBLE_TO_WORD,
133 DOUBLE_TO_LONG,
134
135 LONG_TO_SINGLE,
136 LONG_TO_DOUBLE,
137 LONG_TO_WORD,
138 LONG_TO_PS,
139
140 WORD_TO_SINGLE,
141 WORD_TO_DOUBLE,
142 WORD_TO_LONG,
143 WORD_TO_PS,
144
145 PL_TO_SINGLE,
146 PU_TO_SINGLE
147 };
148
149 //used in FP convert & round function
150 enum RoundMode{
151 RND_ZERO,
152 RND_DOWN,
153 RND_UP,
154 RND_NEAREST
155 };
156
157 enum OperatingMode {
158 MODE_USER = 16,
159 MODE_FIQ = 17,
160 MODE_IRQ = 18,
161 MODE_SVC = 19,
162 MODE_MON = 22,
163 MODE_ABORT = 23,
164 MODE_UNDEFINED = 27,
165 MODE_SYSTEM = 31
166 };
167
168 struct CoreSpecific {
169 // Empty for now on the ARM
170 };
171
172} // namespace ArmISA
173
174#endif
|