1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Stephen Hines
29 */
30
31#ifndef __ARCH_ARM_TYPES_HH__
32#define __ARCH_ARM_TYPES_HH__
33
| 1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Stephen Hines
29 */
30
31#ifndef __ARCH_ARM_TYPES_HH__
32#define __ARCH_ARM_TYPES_HH__
33
|
| 34#include "base/bitunion.hh"
|
34#include "base/types.hh"
35
36namespace ArmISA
37{
38 typedef uint32_t MachInst;
| 35#include "base/types.hh"
36
37namespace ArmISA
38{
39 typedef uint32_t MachInst;
|
39 typedef uint64_t ExtMachInst;
| 40
41 BitUnion32(ExtMachInst)
42 // All the different types of opcode fields.
43 Bitfield<27, 25> opcode;
44 Bitfield<27, 25> opcode27_25;
45 Bitfield<24, 21> opcode24_21;
46 Bitfield<24, 23> opcode24_23;
47 Bitfield<24> opcode24;
48 Bitfield<23, 20> opcode23_20;
49 Bitfield<23, 21> opcode23_21;
50 Bitfield<23> opcode23;
51 Bitfield<22, 8> opcode22_8;
52 Bitfield<22, 21> opcode22_21;
53 Bitfield<22> opcode22;
54 Bitfield<21, 20> opcode21_20;
55 Bitfield<20> opcode20;
56 Bitfield<19, 18> opcode19_18;
57 Bitfield<19> opcode19;
58 Bitfield<15, 12> opcode15_12;
59 Bitfield<15> opcode15;
60 Bitfield<9> opcode9;
61 Bitfield<7, 4> opcode7_4;
62 Bitfield<7, 5> opcode7_5;
63 Bitfield<7, 6> opcode7_6;
64 Bitfield<7> opcode7;
65 Bitfield<6, 5> opcode6_5;
66 Bitfield<6> opcode6;
67 Bitfield<5> opcode5;
68 Bitfield<4> opcode4;
69
70 Bitfield<31, 28> condCode;
71 Bitfield<20> sField;
72 Bitfield<19, 16> rn;
73 Bitfield<15, 12> rd;
74 Bitfield<11, 7> shiftSize;
75 Bitfield<6, 5> shift;
76 Bitfield<3, 0> rm;
77
78 Bitfield<11, 8> rs;
79
80 Bitfield<19, 16> rdup;
81 Bitfield<15, 12> rddn;
82
83 Bitfield<15, 12> rdhi;
84 Bitfield<11, 8> rdlo;
85
86 Bitfield<23> uField;
87
88 SubBitUnion(puswl, 24, 20)
89 Bitfield<24> prepost;
90 Bitfield<23> up;
91 Bitfield<22> psruser;
92 Bitfield<21> writeback;
93 Bitfield<20> loadOp;
94 EndSubBitUnion(puswl)
95
96 Bitfield<24, 20> pubwl;
97 Bitfield<24, 20> puiwl;
98 Bitfield<22> byteAccess;
99
100 Bitfield<23, 20> luas;
101
102 SubBitUnion(imm, 7, 0)
103 Bitfield<7, 4> imm7_4;
104 Bitfield<3, 0> imm3_0;
105 EndSubBitUnion(imm)
106
107 SubBitUnion(msr, 19, 16)
108 Bitfield<19> f;
109 Bitfield<18> s;
110 Bitfield<17> x;
111 Bitfield<16> c;
112 EndSubBitUnion(msr)
113
114 Bitfield<6> y;
115 Bitfield<5> x;
116
117 Bitfield<15, 4> immed15_4;
118
119 Bitfield<21> wField;
120
121 Bitfield<11, 8> rotate;
122 Bitfield<7, 0> immed7_0;
123
124 Bitfield<21> tField;
125 Bitfield<11, 0> immed11_0;
126
127 Bitfield<20, 16> immed20_16;
128 Bitfield<19, 16> immed19_16;
129
130 Bitfield<11, 8> immedHi11_8;
131 Bitfield<3, 0> immedLo3_0;
132
133 Bitfield<11, 10> rot;
134
135 Bitfield<5> rField;
136
137 Bitfield<22> caret;
138 Bitfield<15, 0> regList;
139
140 Bitfield<23, 0> offset;
141 Bitfield<11, 8> copro;
142 Bitfield<7, 4> op1_7_4;
143 Bitfield<3, 0> cm;
144
145 Bitfield<22> lField;
146 Bitfield<15, 12> cd;
147 Bitfield<7, 0> option;
148
149 Bitfield<23, 20> op1_23_20;
150 Bitfield<19, 16> cn;
151 Bitfield<7, 5> op2_7_5;
152
153 Bitfield<23, 21> op1_23_21;
154
155 Bitfield<23, 0> immed23_0;
156 Bitfield<17> mField;
157 Bitfield<8> aField;
158 Bitfield<7> iField;
159 Bitfield<6> fField;
160 Bitfield<4, 0> mode;
161
162 Bitfield<24> aBlx;
163
164 Bitfield<11, 8> cpNum;
165 Bitfield<18, 16> fn;
166 Bitfield<14, 12> fd;
167 Bitfield<3> fpRegImm;
168 Bitfield<3, 0> fm;
169 Bitfield<2, 0> fpImm;
170 Bitfield<24, 20> punwl;
171
172 Bitfield<7, 0> m5Func;
173 EndBitUnion(ExtMachInst)
174
|
40 typedef uint8_t RegIndex;
41
42 typedef uint64_t IntReg;
43 typedef uint64_t LargestRead;
44 // Need to use 64 bits to make sure that read requests get handled properly
45
46 // floating point register file entry type
47 typedef uint32_t FloatReg32;
48 typedef uint64_t FloatReg64;
49 typedef uint64_t FloatRegBits;
50
51 typedef double FloatRegVal;
52 typedef double FloatReg;
53
54 // cop-0/cop-1 system control register
55 typedef uint64_t MiscReg;
56
57 typedef union {
58 IntReg intreg;
59 FloatReg fpreg;
60 MiscReg ctrlreg;
61 } AnyReg;
62
63 typedef int RegContextParam;
64 typedef int RegContextVal;
65
66 //used in FP convert & round function
67 enum ConvertType{
68 SINGLE_TO_DOUBLE,
69 SINGLE_TO_WORD,
70 SINGLE_TO_LONG,
71
72 DOUBLE_TO_SINGLE,
73 DOUBLE_TO_WORD,
74 DOUBLE_TO_LONG,
75
76 LONG_TO_SINGLE,
77 LONG_TO_DOUBLE,
78 LONG_TO_WORD,
79 LONG_TO_PS,
80
81 WORD_TO_SINGLE,
82 WORD_TO_DOUBLE,
83 WORD_TO_LONG,
84 WORD_TO_PS,
85
86 PL_TO_SINGLE,
87 PU_TO_SINGLE
88 };
89
90 //used in FP convert & round function
91 enum RoundMode{
92 RND_ZERO,
93 RND_DOWN,
94 RND_UP,
95 RND_NEAREST
96 };
97
98 enum OperatingMode {
99 MODE_USER = 16,
100 MODE_FIQ = 17,
101 MODE_IRQ = 18,
102 MODE_SVC = 19,
103 MODE_ABORT = 23,
104 MODE_UNDEFINED = 27,
105 MODE_SYSTEM = 31
106 };
107
108 struct CoreSpecific {
109 // Empty for now on the ARM
110 };
111
112} // namespace ArmISA
113
114#endif
| 175 typedef uint8_t RegIndex;
176
177 typedef uint64_t IntReg;
178 typedef uint64_t LargestRead;
179 // Need to use 64 bits to make sure that read requests get handled properly
180
181 // floating point register file entry type
182 typedef uint32_t FloatReg32;
183 typedef uint64_t FloatReg64;
184 typedef uint64_t FloatRegBits;
185
186 typedef double FloatRegVal;
187 typedef double FloatReg;
188
189 // cop-0/cop-1 system control register
190 typedef uint64_t MiscReg;
191
192 typedef union {
193 IntReg intreg;
194 FloatReg fpreg;
195 MiscReg ctrlreg;
196 } AnyReg;
197
198 typedef int RegContextParam;
199 typedef int RegContextVal;
200
201 //used in FP convert & round function
202 enum ConvertType{
203 SINGLE_TO_DOUBLE,
204 SINGLE_TO_WORD,
205 SINGLE_TO_LONG,
206
207 DOUBLE_TO_SINGLE,
208 DOUBLE_TO_WORD,
209 DOUBLE_TO_LONG,
210
211 LONG_TO_SINGLE,
212 LONG_TO_DOUBLE,
213 LONG_TO_WORD,
214 LONG_TO_PS,
215
216 WORD_TO_SINGLE,
217 WORD_TO_DOUBLE,
218 WORD_TO_LONG,
219 WORD_TO_PS,
220
221 PL_TO_SINGLE,
222 PU_TO_SINGLE
223 };
224
225 //used in FP convert & round function
226 enum RoundMode{
227 RND_ZERO,
228 RND_DOWN,
229 RND_UP,
230 RND_NEAREST
231 };
232
233 enum OperatingMode {
234 MODE_USER = 16,
235 MODE_FIQ = 17,
236 MODE_IRQ = 18,
237 MODE_SVC = 19,
238 MODE_ABORT = 23,
239 MODE_UNDEFINED = 27,
240 MODE_SYSTEM = 31
241 };
242
243 struct CoreSpecific {
244 // Empty for now on the ARM
245 };
246
247} // namespace ArmISA
248
249#endif
|