1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
46#include "arch/generic/types.hh"
47#include "base/bitunion.hh"
| 1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
46#include "arch/generic/types.hh"
47#include "base/bitunion.hh"
|
48#include "base/hashmap.hh"
| |
49#include "base/misc.hh"
50#include "base/types.hh"
51#include "debug/Decoder.hh"
52
53namespace ArmISA
54{
55 typedef uint32_t MachInst;
56
57 BitUnion8(ITSTATE)
58 /* Note that the split (cond, mask) below is not as in ARM ARM.
59 * But it is more convenient for simulation. The condition
60 * is always the concatenation of the top 3 bits and the next bit,
61 * which applies when one of the bottom 4 bits is set.
62 * Refer to predecoder.cc for the use case.
63 */
64 Bitfield<7, 4> cond;
65 Bitfield<3, 0> mask;
66 // Bitfields for moving to/from CPSR
67 Bitfield<7, 2> top6;
68 Bitfield<1, 0> bottom2;
69 EndBitUnion(ITSTATE)
70
71 BitUnion64(ExtMachInst)
72 // Decoder state
73 Bitfield<63, 62> decoderFault; // See DecoderFault
74
75 // ITSTATE bits
76 Bitfield<55, 48> itstate;
77 Bitfield<55, 52> itstateCond;
78 Bitfield<51, 48> itstateMask;
79
80 // FPSCR fields
81 Bitfield<41, 40> fpscrStride;
82 Bitfield<39, 37> fpscrLen;
83
84 // Bitfields to select mode.
85 Bitfield<36> thumb;
86 Bitfield<35> bigThumb;
87 Bitfield<34> aarch64;
88
89 // Made up bitfields that make life easier.
90 Bitfield<33> sevenAndFour;
91 Bitfield<32> isMisc;
92
93 uint32_t instBits;
94
95 // All the different types of opcode fields.
96 Bitfield<27, 25> encoding;
97 Bitfield<25> useImm;
98 Bitfield<24, 21> opcode;
99 Bitfield<24, 20> mediaOpcode;
100 Bitfield<24> opcode24;
101 Bitfield<24, 23> opcode24_23;
102 Bitfield<23, 20> opcode23_20;
103 Bitfield<23, 21> opcode23_21;
104 Bitfield<20> opcode20;
105 Bitfield<22> opcode22;
106 Bitfield<19, 16> opcode19_16;
107 Bitfield<19> opcode19;
108 Bitfield<18> opcode18;
109 Bitfield<15, 12> opcode15_12;
110 Bitfield<15> opcode15;
111 Bitfield<7, 4> miscOpcode;
112 Bitfield<7,5> opc2;
113 Bitfield<7> opcode7;
114 Bitfield<6> opcode6;
115 Bitfield<4> opcode4;
116
117 Bitfield<31, 28> condCode;
118 Bitfield<20> sField;
119 Bitfield<19, 16> rn;
120 Bitfield<15, 12> rd;
121 Bitfield<15, 12> rt;
122 Bitfield<11, 7> shiftSize;
123 Bitfield<6, 5> shift;
124 Bitfield<3, 0> rm;
125
126 Bitfield<11, 8> rs;
127
128 SubBitUnion(puswl, 24, 20)
129 Bitfield<24> prepost;
130 Bitfield<23> up;
131 Bitfield<22> psruser;
132 Bitfield<21> writeback;
133 Bitfield<20> loadOp;
134 EndSubBitUnion(puswl)
135
136 Bitfield<24, 20> pubwl;
137
138 Bitfield<7, 0> imm;
139
140 Bitfield<11, 8> rotate;
141
142 Bitfield<11, 0> immed11_0;
143 Bitfield<7, 0> immed7_0;
144
145 Bitfield<11, 8> immedHi11_8;
146 Bitfield<3, 0> immedLo3_0;
147
148 Bitfield<15, 0> regList;
149
150 Bitfield<23, 0> offset;
151
152 Bitfield<23, 0> immed23_0;
153
154 Bitfield<11, 8> cpNum;
155 Bitfield<18, 16> fn;
156 Bitfield<14, 12> fd;
157 Bitfield<3> fpRegImm;
158 Bitfield<3, 0> fm;
159 Bitfield<2, 0> fpImm;
160 Bitfield<24, 20> punwl;
161
162 Bitfield<15, 8> m5Func;
163
164 // 16 bit thumb bitfields
165 Bitfield<15, 13> topcode15_13;
166 Bitfield<13, 11> topcode13_11;
167 Bitfield<12, 11> topcode12_11;
168 Bitfield<12, 10> topcode12_10;
169 Bitfield<11, 9> topcode11_9;
170 Bitfield<11, 8> topcode11_8;
171 Bitfield<10, 9> topcode10_9;
172 Bitfield<10, 8> topcode10_8;
173 Bitfield<9, 6> topcode9_6;
174 Bitfield<7> topcode7;
175 Bitfield<7, 6> topcode7_6;
176 Bitfield<7, 5> topcode7_5;
177 Bitfield<7, 4> topcode7_4;
178 Bitfield<3, 0> topcode3_0;
179
180 // 32 bit thumb bitfields
181 Bitfield<28, 27> htopcode12_11;
182 Bitfield<26, 25> htopcode10_9;
183 Bitfield<25> htopcode9;
184 Bitfield<25, 24> htopcode9_8;
185 Bitfield<25, 21> htopcode9_5;
186 Bitfield<25, 20> htopcode9_4;
187 Bitfield<24> htopcode8;
188 Bitfield<24, 23> htopcode8_7;
189 Bitfield<24, 22> htopcode8_6;
190 Bitfield<24, 21> htopcode8_5;
191 Bitfield<23> htopcode7;
192 Bitfield<23, 21> htopcode7_5;
193 Bitfield<22> htopcode6;
194 Bitfield<22, 21> htopcode6_5;
195 Bitfield<21, 20> htopcode5_4;
196 Bitfield<20> htopcode4;
197
198 Bitfield<19, 16> htrn;
199 Bitfield<20> hts;
200
201 Bitfield<15> ltopcode15;
202 Bitfield<11, 8> ltopcode11_8;
203 Bitfield<7, 6> ltopcode7_6;
204 Bitfield<7, 4> ltopcode7_4;
205 Bitfield<4> ltopcode4;
206
207 Bitfield<11, 8> ltrd;
208 Bitfield<11, 8> ltcoproc;
209 EndBitUnion(ExtMachInst)
210
211 class PCState : public GenericISA::UPCState<MachInst>
212 {
213 protected:
214
215 typedef GenericISA::UPCState<MachInst> Base;
216
217 enum FlagBits {
218 ThumbBit = (1 << 0),
219 JazelleBit = (1 << 1),
220 AArch64Bit = (1 << 2)
221 };
222 uint8_t flags;
223 uint8_t nextFlags;
224 uint8_t _itstate;
225 uint8_t _nextItstate;
226 uint8_t _size;
227 public:
228 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
229 _size(0)
230 {}
231
232 void
233 set(Addr val)
234 {
235 Base::set(val);
236 npc(val + (thumb() ? 2 : 4));
237 }
238
239 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
240 _nextItstate(0), _size(0)
241 { set(val); }
242
243 bool
244 thumb() const
245 {
246 return flags & ThumbBit;
247 }
248
249 void
250 thumb(bool val)
251 {
252 if (val)
253 flags |= ThumbBit;
254 else
255 flags &= ~ThumbBit;
256 }
257
258 bool
259 nextThumb() const
260 {
261 return nextFlags & ThumbBit;
262 }
263
264 void
265 nextThumb(bool val)
266 {
267 if (val)
268 nextFlags |= ThumbBit;
269 else
270 nextFlags &= ~ThumbBit;
271 }
272
273 void size(uint8_t s) { _size = s; }
274 uint8_t size() const { return _size; }
275
276 bool
277 branching() const
278 {
279 return ((this->pc() + this->size()) != this->npc());
280 }
281
282
283 bool
284 jazelle() const
285 {
286 return flags & JazelleBit;
287 }
288
289 void
290 jazelle(bool val)
291 {
292 if (val)
293 flags |= JazelleBit;
294 else
295 flags &= ~JazelleBit;
296 }
297
298 bool
299 nextJazelle() const
300 {
301 return nextFlags & JazelleBit;
302 }
303
304 void
305 nextJazelle(bool val)
306 {
307 if (val)
308 nextFlags |= JazelleBit;
309 else
310 nextFlags &= ~JazelleBit;
311 }
312
313 bool
314 aarch64() const
315 {
316 return flags & AArch64Bit;
317 }
318
319 void
320 aarch64(bool val)
321 {
322 if (val)
323 flags |= AArch64Bit;
324 else
325 flags &= ~AArch64Bit;
326 }
327
328 bool
329 nextAArch64() const
330 {
331 return nextFlags & AArch64Bit;
332 }
333
334 void
335 nextAArch64(bool val)
336 {
337 if (val)
338 nextFlags |= AArch64Bit;
339 else
340 nextFlags &= ~AArch64Bit;
341 }
342
343
344 uint8_t
345 itstate() const
346 {
347 return _itstate;
348 }
349
350 void
351 itstate(uint8_t value)
352 {
353 _itstate = value;
354 }
355
356 uint8_t
357 nextItstate() const
358 {
359 return _nextItstate;
360 }
361
362 void
363 nextItstate(uint8_t value)
364 {
365 _nextItstate = value;
366 }
367
368 void
369 advance()
370 {
371 Base::advance();
372 flags = nextFlags;
373 npc(pc() + (thumb() ? 2 : 4));
374
375 if (_nextItstate) {
376 _itstate = _nextItstate;
377 _nextItstate = 0;
378 } else if (_itstate) {
379 ITSTATE it = _itstate;
380 uint8_t cond_mask = it.mask;
381 uint8_t thumb_cond = it.cond;
382 DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
383 thumb_cond, cond_mask);
384 cond_mask <<= 1;
385 uint8_t new_bit = bits(cond_mask, 4);
386 cond_mask &= mask(4);
387 if (cond_mask == 0)
388 thumb_cond = 0;
389 else
390 replaceBits(thumb_cond, 0, new_bit);
391 DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
392 thumb_cond, cond_mask);
393 it.mask = cond_mask;
394 it.cond = thumb_cond;
395 _itstate = it;
396 }
397 }
398
399 void
400 uEnd()
401 {
402 advance();
403 upc(0);
404 nupc(1);
405 }
406
407 Addr
408 instPC() const
409 {
410 return pc() + (thumb() ? 4 : 8);
411 }
412
413 void
414 instNPC(Addr val)
415 {
416 // @todo: review this when AArch32/64 interprocessing is
417 // supported
418 if (aarch64())
419 npc(val); // AArch64 doesn't force PC alignment, a PC
420 // Alignment Fault can be raised instead
421 else
422 npc(val &~ mask(nextThumb() ? 1 : 2));
423 }
424
425 Addr
426 instNPC() const
427 {
428 return npc();
429 }
430
431 // Perform an interworking branch.
432 void
433 instIWNPC(Addr val)
434 {
435 bool thumbEE = (thumb() && jazelle());
436
437 Addr newPC = val;
438 if (thumbEE) {
439 if (bits(newPC, 0)) {
440 newPC = newPC & ~mask(1);
441 } // else we have a bad interworking address; do not call
442 // panic() since the instruction could be executed
443 // speculatively
444 } else {
445 if (bits(newPC, 0)) {
446 nextThumb(true);
447 newPC = newPC & ~mask(1);
448 } else if (!bits(newPC, 1)) {
449 nextThumb(false);
450 } else {
451 // This state is UNPREDICTABLE in the ARM architecture
452 // The easy thing to do is just mask off the bit and
453 // stay in the current mode, so we'll do that.
454 newPC &= ~mask(2);
455 }
456 }
457 npc(newPC);
458 }
459
460 // Perform an interworking branch in ARM mode, a regular branch
461 // otherwise.
462 void
463 instAIWNPC(Addr val)
464 {
465 if (!thumb() && !jazelle())
466 instIWNPC(val);
467 else
468 instNPC(val);
469 }
470
471 bool
472 operator == (const PCState &opc) const
473 {
474 return Base::operator == (opc) &&
475 flags == opc.flags && nextFlags == opc.nextFlags &&
476 _itstate == opc._itstate && _nextItstate == opc._nextItstate;
477 }
478
479 bool
480 operator != (const PCState &opc) const
481 {
482 return !(*this == opc);
483 }
484
485 void
| 48#include "base/misc.hh"
49#include "base/types.hh"
50#include "debug/Decoder.hh"
51
52namespace ArmISA
53{
54 typedef uint32_t MachInst;
55
56 BitUnion8(ITSTATE)
57 /* Note that the split (cond, mask) below is not as in ARM ARM.
58 * But it is more convenient for simulation. The condition
59 * is always the concatenation of the top 3 bits and the next bit,
60 * which applies when one of the bottom 4 bits is set.
61 * Refer to predecoder.cc for the use case.
62 */
63 Bitfield<7, 4> cond;
64 Bitfield<3, 0> mask;
65 // Bitfields for moving to/from CPSR
66 Bitfield<7, 2> top6;
67 Bitfield<1, 0> bottom2;
68 EndBitUnion(ITSTATE)
69
70 BitUnion64(ExtMachInst)
71 // Decoder state
72 Bitfield<63, 62> decoderFault; // See DecoderFault
73
74 // ITSTATE bits
75 Bitfield<55, 48> itstate;
76 Bitfield<55, 52> itstateCond;
77 Bitfield<51, 48> itstateMask;
78
79 // FPSCR fields
80 Bitfield<41, 40> fpscrStride;
81 Bitfield<39, 37> fpscrLen;
82
83 // Bitfields to select mode.
84 Bitfield<36> thumb;
85 Bitfield<35> bigThumb;
86 Bitfield<34> aarch64;
87
88 // Made up bitfields that make life easier.
89 Bitfield<33> sevenAndFour;
90 Bitfield<32> isMisc;
91
92 uint32_t instBits;
93
94 // All the different types of opcode fields.
95 Bitfield<27, 25> encoding;
96 Bitfield<25> useImm;
97 Bitfield<24, 21> opcode;
98 Bitfield<24, 20> mediaOpcode;
99 Bitfield<24> opcode24;
100 Bitfield<24, 23> opcode24_23;
101 Bitfield<23, 20> opcode23_20;
102 Bitfield<23, 21> opcode23_21;
103 Bitfield<20> opcode20;
104 Bitfield<22> opcode22;
105 Bitfield<19, 16> opcode19_16;
106 Bitfield<19> opcode19;
107 Bitfield<18> opcode18;
108 Bitfield<15, 12> opcode15_12;
109 Bitfield<15> opcode15;
110 Bitfield<7, 4> miscOpcode;
111 Bitfield<7,5> opc2;
112 Bitfield<7> opcode7;
113 Bitfield<6> opcode6;
114 Bitfield<4> opcode4;
115
116 Bitfield<31, 28> condCode;
117 Bitfield<20> sField;
118 Bitfield<19, 16> rn;
119 Bitfield<15, 12> rd;
120 Bitfield<15, 12> rt;
121 Bitfield<11, 7> shiftSize;
122 Bitfield<6, 5> shift;
123 Bitfield<3, 0> rm;
124
125 Bitfield<11, 8> rs;
126
127 SubBitUnion(puswl, 24, 20)
128 Bitfield<24> prepost;
129 Bitfield<23> up;
130 Bitfield<22> psruser;
131 Bitfield<21> writeback;
132 Bitfield<20> loadOp;
133 EndSubBitUnion(puswl)
134
135 Bitfield<24, 20> pubwl;
136
137 Bitfield<7, 0> imm;
138
139 Bitfield<11, 8> rotate;
140
141 Bitfield<11, 0> immed11_0;
142 Bitfield<7, 0> immed7_0;
143
144 Bitfield<11, 8> immedHi11_8;
145 Bitfield<3, 0> immedLo3_0;
146
147 Bitfield<15, 0> regList;
148
149 Bitfield<23, 0> offset;
150
151 Bitfield<23, 0> immed23_0;
152
153 Bitfield<11, 8> cpNum;
154 Bitfield<18, 16> fn;
155 Bitfield<14, 12> fd;
156 Bitfield<3> fpRegImm;
157 Bitfield<3, 0> fm;
158 Bitfield<2, 0> fpImm;
159 Bitfield<24, 20> punwl;
160
161 Bitfield<15, 8> m5Func;
162
163 // 16 bit thumb bitfields
164 Bitfield<15, 13> topcode15_13;
165 Bitfield<13, 11> topcode13_11;
166 Bitfield<12, 11> topcode12_11;
167 Bitfield<12, 10> topcode12_10;
168 Bitfield<11, 9> topcode11_9;
169 Bitfield<11, 8> topcode11_8;
170 Bitfield<10, 9> topcode10_9;
171 Bitfield<10, 8> topcode10_8;
172 Bitfield<9, 6> topcode9_6;
173 Bitfield<7> topcode7;
174 Bitfield<7, 6> topcode7_6;
175 Bitfield<7, 5> topcode7_5;
176 Bitfield<7, 4> topcode7_4;
177 Bitfield<3, 0> topcode3_0;
178
179 // 32 bit thumb bitfields
180 Bitfield<28, 27> htopcode12_11;
181 Bitfield<26, 25> htopcode10_9;
182 Bitfield<25> htopcode9;
183 Bitfield<25, 24> htopcode9_8;
184 Bitfield<25, 21> htopcode9_5;
185 Bitfield<25, 20> htopcode9_4;
186 Bitfield<24> htopcode8;
187 Bitfield<24, 23> htopcode8_7;
188 Bitfield<24, 22> htopcode8_6;
189 Bitfield<24, 21> htopcode8_5;
190 Bitfield<23> htopcode7;
191 Bitfield<23, 21> htopcode7_5;
192 Bitfield<22> htopcode6;
193 Bitfield<22, 21> htopcode6_5;
194 Bitfield<21, 20> htopcode5_4;
195 Bitfield<20> htopcode4;
196
197 Bitfield<19, 16> htrn;
198 Bitfield<20> hts;
199
200 Bitfield<15> ltopcode15;
201 Bitfield<11, 8> ltopcode11_8;
202 Bitfield<7, 6> ltopcode7_6;
203 Bitfield<7, 4> ltopcode7_4;
204 Bitfield<4> ltopcode4;
205
206 Bitfield<11, 8> ltrd;
207 Bitfield<11, 8> ltcoproc;
208 EndBitUnion(ExtMachInst)
209
210 class PCState : public GenericISA::UPCState<MachInst>
211 {
212 protected:
213
214 typedef GenericISA::UPCState<MachInst> Base;
215
216 enum FlagBits {
217 ThumbBit = (1 << 0),
218 JazelleBit = (1 << 1),
219 AArch64Bit = (1 << 2)
220 };
221 uint8_t flags;
222 uint8_t nextFlags;
223 uint8_t _itstate;
224 uint8_t _nextItstate;
225 uint8_t _size;
226 public:
227 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
228 _size(0)
229 {}
230
231 void
232 set(Addr val)
233 {
234 Base::set(val);
235 npc(val + (thumb() ? 2 : 4));
236 }
237
238 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
239 _nextItstate(0), _size(0)
240 { set(val); }
241
242 bool
243 thumb() const
244 {
245 return flags & ThumbBit;
246 }
247
248 void
249 thumb(bool val)
250 {
251 if (val)
252 flags |= ThumbBit;
253 else
254 flags &= ~ThumbBit;
255 }
256
257 bool
258 nextThumb() const
259 {
260 return nextFlags & ThumbBit;
261 }
262
263 void
264 nextThumb(bool val)
265 {
266 if (val)
267 nextFlags |= ThumbBit;
268 else
269 nextFlags &= ~ThumbBit;
270 }
271
272 void size(uint8_t s) { _size = s; }
273 uint8_t size() const { return _size; }
274
275 bool
276 branching() const
277 {
278 return ((this->pc() + this->size()) != this->npc());
279 }
280
281
282 bool
283 jazelle() const
284 {
285 return flags & JazelleBit;
286 }
287
288 void
289 jazelle(bool val)
290 {
291 if (val)
292 flags |= JazelleBit;
293 else
294 flags &= ~JazelleBit;
295 }
296
297 bool
298 nextJazelle() const
299 {
300 return nextFlags & JazelleBit;
301 }
302
303 void
304 nextJazelle(bool val)
305 {
306 if (val)
307 nextFlags |= JazelleBit;
308 else
309 nextFlags &= ~JazelleBit;
310 }
311
312 bool
313 aarch64() const
314 {
315 return flags & AArch64Bit;
316 }
317
318 void
319 aarch64(bool val)
320 {
321 if (val)
322 flags |= AArch64Bit;
323 else
324 flags &= ~AArch64Bit;
325 }
326
327 bool
328 nextAArch64() const
329 {
330 return nextFlags & AArch64Bit;
331 }
332
333 void
334 nextAArch64(bool val)
335 {
336 if (val)
337 nextFlags |= AArch64Bit;
338 else
339 nextFlags &= ~AArch64Bit;
340 }
341
342
343 uint8_t
344 itstate() const
345 {
346 return _itstate;
347 }
348
349 void
350 itstate(uint8_t value)
351 {
352 _itstate = value;
353 }
354
355 uint8_t
356 nextItstate() const
357 {
358 return _nextItstate;
359 }
360
361 void
362 nextItstate(uint8_t value)
363 {
364 _nextItstate = value;
365 }
366
367 void
368 advance()
369 {
370 Base::advance();
371 flags = nextFlags;
372 npc(pc() + (thumb() ? 2 : 4));
373
374 if (_nextItstate) {
375 _itstate = _nextItstate;
376 _nextItstate = 0;
377 } else if (_itstate) {
378 ITSTATE it = _itstate;
379 uint8_t cond_mask = it.mask;
380 uint8_t thumb_cond = it.cond;
381 DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
382 thumb_cond, cond_mask);
383 cond_mask <<= 1;
384 uint8_t new_bit = bits(cond_mask, 4);
385 cond_mask &= mask(4);
386 if (cond_mask == 0)
387 thumb_cond = 0;
388 else
389 replaceBits(thumb_cond, 0, new_bit);
390 DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
391 thumb_cond, cond_mask);
392 it.mask = cond_mask;
393 it.cond = thumb_cond;
394 _itstate = it;
395 }
396 }
397
398 void
399 uEnd()
400 {
401 advance();
402 upc(0);
403 nupc(1);
404 }
405
406 Addr
407 instPC() const
408 {
409 return pc() + (thumb() ? 4 : 8);
410 }
411
412 void
413 instNPC(Addr val)
414 {
415 // @todo: review this when AArch32/64 interprocessing is
416 // supported
417 if (aarch64())
418 npc(val); // AArch64 doesn't force PC alignment, a PC
419 // Alignment Fault can be raised instead
420 else
421 npc(val &~ mask(nextThumb() ? 1 : 2));
422 }
423
424 Addr
425 instNPC() const
426 {
427 return npc();
428 }
429
430 // Perform an interworking branch.
431 void
432 instIWNPC(Addr val)
433 {
434 bool thumbEE = (thumb() && jazelle());
435
436 Addr newPC = val;
437 if (thumbEE) {
438 if (bits(newPC, 0)) {
439 newPC = newPC & ~mask(1);
440 } // else we have a bad interworking address; do not call
441 // panic() since the instruction could be executed
442 // speculatively
443 } else {
444 if (bits(newPC, 0)) {
445 nextThumb(true);
446 newPC = newPC & ~mask(1);
447 } else if (!bits(newPC, 1)) {
448 nextThumb(false);
449 } else {
450 // This state is UNPREDICTABLE in the ARM architecture
451 // The easy thing to do is just mask off the bit and
452 // stay in the current mode, so we'll do that.
453 newPC &= ~mask(2);
454 }
455 }
456 npc(newPC);
457 }
458
459 // Perform an interworking branch in ARM mode, a regular branch
460 // otherwise.
461 void
462 instAIWNPC(Addr val)
463 {
464 if (!thumb() && !jazelle())
465 instIWNPC(val);
466 else
467 instNPC(val);
468 }
469
470 bool
471 operator == (const PCState &opc) const
472 {
473 return Base::operator == (opc) &&
474 flags == opc.flags && nextFlags == opc.nextFlags &&
475 _itstate == opc._itstate && _nextItstate == opc._nextItstate;
476 }
477
478 bool
479 operator != (const PCState &opc) const
480 {
481 return !(*this == opc);
482 }
483
484 void
|
486 serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
| 485 serialize(CheckpointOut &cp) const override
|
487 {
488 Base::serialize(cp);
489 SERIALIZE_SCALAR(flags);
490 SERIALIZE_SCALAR(_size);
491 SERIALIZE_SCALAR(nextFlags);
492 SERIALIZE_SCALAR(_itstate);
493 SERIALIZE_SCALAR(_nextItstate);
494 }
495
496 void
| 486 {
487 Base::serialize(cp);
488 SERIALIZE_SCALAR(flags);
489 SERIALIZE_SCALAR(_size);
490 SERIALIZE_SCALAR(nextFlags);
491 SERIALIZE_SCALAR(_itstate);
492 SERIALIZE_SCALAR(_nextItstate);
493 }
494
495 void
|
497 unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
| 496 unserialize(CheckpointIn &cp) override
|
498 {
499 Base::unserialize(cp);
500 UNSERIALIZE_SCALAR(flags);
501 UNSERIALIZE_SCALAR(_size);
502 UNSERIALIZE_SCALAR(nextFlags);
503 UNSERIALIZE_SCALAR(_itstate);
504 UNSERIALIZE_SCALAR(_nextItstate);
505 }
506 };
507
508 // Shift types for ARM instructions
509 enum ArmShiftType {
510 LSL = 0,
511 LSR,
512 ASR,
513 ROR
514 };
515
516 // Extension types for ARM instructions
517 enum ArmExtendType {
518 UXTB = 0,
519 UXTH = 1,
520 UXTW = 2,
521 UXTX = 3,
522 SXTB = 4,
523 SXTH = 5,
524 SXTW = 6,
525 SXTX = 7
526 };
527
528 typedef uint64_t LargestRead;
529 // Need to use 64 bits to make sure that read requests get handled properly
530
531 typedef int RegContextParam;
532 typedef int RegContextVal;
533
534 //used in FP convert & round function
535 enum ConvertType{
536 SINGLE_TO_DOUBLE,
537 SINGLE_TO_WORD,
538 SINGLE_TO_LONG,
539
540 DOUBLE_TO_SINGLE,
541 DOUBLE_TO_WORD,
542 DOUBLE_TO_LONG,
543
544 LONG_TO_SINGLE,
545 LONG_TO_DOUBLE,
546 LONG_TO_WORD,
547 LONG_TO_PS,
548
549 WORD_TO_SINGLE,
550 WORD_TO_DOUBLE,
551 WORD_TO_LONG,
552 WORD_TO_PS,
553
554 PL_TO_SINGLE,
555 PU_TO_SINGLE
556 };
557
558 //used in FP convert & round function
559 enum RoundMode{
560 RND_ZERO,
561 RND_DOWN,
562 RND_UP,
563 RND_NEAREST
564 };
565
566 enum ExceptionLevel {
567 EL0 = 0,
568 EL1,
569 EL2,
570 EL3
571 };
572
573 enum OperatingMode {
574 MODE_EL0T = 0x0,
575 MODE_EL1T = 0x4,
576 MODE_EL1H = 0x5,
577 MODE_EL2T = 0x8,
578 MODE_EL2H = 0x9,
579 MODE_EL3T = 0xC,
580 MODE_EL3H = 0xD,
581 MODE_USER = 16,
582 MODE_FIQ = 17,
583 MODE_IRQ = 18,
584 MODE_SVC = 19,
585 MODE_MON = 22,
586 MODE_ABORT = 23,
587 MODE_HYP = 26,
588 MODE_UNDEFINED = 27,
589 MODE_SYSTEM = 31,
590 MODE_MAXMODE = MODE_SYSTEM
591 };
592
593 enum ExceptionClass {
594 EC_INVALID = -1,
595 EC_UNKNOWN = 0x0,
596 EC_TRAPPED_WFI_WFE = 0x1,
597 EC_TRAPPED_CP15_MCR_MRC = 0x3,
598 EC_TRAPPED_CP15_MCRR_MRRC = 0x4,
599 EC_TRAPPED_CP14_MCR_MRC = 0x5,
600 EC_TRAPPED_CP14_LDC_STC = 0x6,
601 EC_TRAPPED_HCPTR = 0x7,
602 EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias
603 EC_TRAPPED_CP10_MRC_VMRS = 0x8,
604 EC_TRAPPED_BXJ = 0xA,
605 EC_TRAPPED_CP14_MCRR_MRRC = 0xC,
606 EC_ILLEGAL_INST = 0xE,
607 EC_SVC_TO_HYP = 0x11,
608 EC_SVC = 0x11, // AArch64 alias
609 EC_HVC = 0x12,
610 EC_SMC_TO_HYP = 0x13,
611 EC_SMC = 0x13, // AArch64 alias
612 EC_SVC_64 = 0x15,
613 EC_HVC_64 = 0x16,
614 EC_SMC_64 = 0x17,
615 EC_TRAPPED_MSR_MRS_64 = 0x18,
616 EC_PREFETCH_ABORT_TO_HYP = 0x20,
617 EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias
618 EC_PREFETCH_ABORT_FROM_HYP = 0x21,
619 EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias
620 EC_PC_ALIGNMENT = 0x22,
621 EC_DATA_ABORT_TO_HYP = 0x24,
622 EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias
623 EC_DATA_ABORT_FROM_HYP = 0x25,
624 EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias
625 EC_STACK_PTR_ALIGNMENT = 0x26,
626 EC_FP_EXCEPTION = 0x28,
627 EC_FP_EXCEPTION_64 = 0x2C,
628 EC_SERROR = 0x2F
629 };
630
631 /**
632 * Instruction decoder fault codes in ExtMachInst.
633 */
634 enum DecoderFault : std::uint8_t {
635 OK = 0x0, ///< No fault
636 UNALIGNED = 0x1, ///< Unaligned instruction fault
637
638 PANIC = 0x3, ///< Internal gem5 error
639 };
640
641 BitUnion8(OperatingMode64)
642 Bitfield<0> spX;
643 Bitfield<3, 2> el;
644 Bitfield<4> width;
645 EndBitUnion(OperatingMode64)
646
647 static bool inline
648 opModeIs64(OperatingMode mode)
649 {
650 return ((OperatingMode64)(uint8_t)mode).width == 0;
651 }
652
653 static bool inline
654 opModeIsH(OperatingMode mode)
655 {
656 return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H);
657 }
658
659 static bool inline
660 opModeIsT(OperatingMode mode)
661 {
662 return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T ||
663 mode == MODE_EL3T);
664 }
665
666 static ExceptionLevel inline
667 opModeToEL(OperatingMode mode)
668 {
669 bool aarch32 = ((mode >> 4) & 1) ? true : false;
670 if (aarch32) {
671 switch (mode) {
672 case MODE_USER:
673 return EL0;
674 case MODE_FIQ:
675 case MODE_IRQ:
676 case MODE_SVC:
677 case MODE_ABORT:
678 case MODE_UNDEFINED:
679 case MODE_SYSTEM:
680 return EL1;
681 case MODE_HYP:
682 return EL2;
683 case MODE_MON:
684 return EL3;
685 default:
686 panic("Invalid operating mode: %d", mode);
687 break;
688 }
689 } else {
690 // aarch64
691 return (ExceptionLevel) ((mode >> 2) & 3);
692 }
693 }
694
695 static inline bool
696 badMode(OperatingMode mode)
697 {
698 switch (mode) {
699 case MODE_EL0T:
700 case MODE_EL1T:
701 case MODE_EL1H:
702 case MODE_EL2T:
703 case MODE_EL2H:
704 case MODE_EL3T:
705 case MODE_EL3H:
706 case MODE_USER:
707 case MODE_FIQ:
708 case MODE_IRQ:
709 case MODE_SVC:
710 case MODE_MON:
711 case MODE_ABORT:
712 case MODE_HYP:
713 case MODE_UNDEFINED:
714 case MODE_SYSTEM:
715 return false;
716 default:
717 return true;
718 }
719 }
720
721
722 static inline bool
723 badMode32(OperatingMode mode)
724 {
725 switch (mode) {
726 case MODE_USER:
727 case MODE_FIQ:
728 case MODE_IRQ:
729 case MODE_SVC:
730 case MODE_MON:
731 case MODE_ABORT:
732 case MODE_HYP:
733 case MODE_UNDEFINED:
734 case MODE_SYSTEM:
735 return false;
736 default:
737 return true;
738 }
739 }
740
741} // namespace ArmISA
742
| 497 {
498 Base::unserialize(cp);
499 UNSERIALIZE_SCALAR(flags);
500 UNSERIALIZE_SCALAR(_size);
501 UNSERIALIZE_SCALAR(nextFlags);
502 UNSERIALIZE_SCALAR(_itstate);
503 UNSERIALIZE_SCALAR(_nextItstate);
504 }
505 };
506
507 // Shift types for ARM instructions
508 enum ArmShiftType {
509 LSL = 0,
510 LSR,
511 ASR,
512 ROR
513 };
514
515 // Extension types for ARM instructions
516 enum ArmExtendType {
517 UXTB = 0,
518 UXTH = 1,
519 UXTW = 2,
520 UXTX = 3,
521 SXTB = 4,
522 SXTH = 5,
523 SXTW = 6,
524 SXTX = 7
525 };
526
527 typedef uint64_t LargestRead;
528 // Need to use 64 bits to make sure that read requests get handled properly
529
530 typedef int RegContextParam;
531 typedef int RegContextVal;
532
533 //used in FP convert & round function
534 enum ConvertType{
535 SINGLE_TO_DOUBLE,
536 SINGLE_TO_WORD,
537 SINGLE_TO_LONG,
538
539 DOUBLE_TO_SINGLE,
540 DOUBLE_TO_WORD,
541 DOUBLE_TO_LONG,
542
543 LONG_TO_SINGLE,
544 LONG_TO_DOUBLE,
545 LONG_TO_WORD,
546 LONG_TO_PS,
547
548 WORD_TO_SINGLE,
549 WORD_TO_DOUBLE,
550 WORD_TO_LONG,
551 WORD_TO_PS,
552
553 PL_TO_SINGLE,
554 PU_TO_SINGLE
555 };
556
557 //used in FP convert & round function
558 enum RoundMode{
559 RND_ZERO,
560 RND_DOWN,
561 RND_UP,
562 RND_NEAREST
563 };
564
565 enum ExceptionLevel {
566 EL0 = 0,
567 EL1,
568 EL2,
569 EL3
570 };
571
572 enum OperatingMode {
573 MODE_EL0T = 0x0,
574 MODE_EL1T = 0x4,
575 MODE_EL1H = 0x5,
576 MODE_EL2T = 0x8,
577 MODE_EL2H = 0x9,
578 MODE_EL3T = 0xC,
579 MODE_EL3H = 0xD,
580 MODE_USER = 16,
581 MODE_FIQ = 17,
582 MODE_IRQ = 18,
583 MODE_SVC = 19,
584 MODE_MON = 22,
585 MODE_ABORT = 23,
586 MODE_HYP = 26,
587 MODE_UNDEFINED = 27,
588 MODE_SYSTEM = 31,
589 MODE_MAXMODE = MODE_SYSTEM
590 };
591
592 enum ExceptionClass {
593 EC_INVALID = -1,
594 EC_UNKNOWN = 0x0,
595 EC_TRAPPED_WFI_WFE = 0x1,
596 EC_TRAPPED_CP15_MCR_MRC = 0x3,
597 EC_TRAPPED_CP15_MCRR_MRRC = 0x4,
598 EC_TRAPPED_CP14_MCR_MRC = 0x5,
599 EC_TRAPPED_CP14_LDC_STC = 0x6,
600 EC_TRAPPED_HCPTR = 0x7,
601 EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias
602 EC_TRAPPED_CP10_MRC_VMRS = 0x8,
603 EC_TRAPPED_BXJ = 0xA,
604 EC_TRAPPED_CP14_MCRR_MRRC = 0xC,
605 EC_ILLEGAL_INST = 0xE,
606 EC_SVC_TO_HYP = 0x11,
607 EC_SVC = 0x11, // AArch64 alias
608 EC_HVC = 0x12,
609 EC_SMC_TO_HYP = 0x13,
610 EC_SMC = 0x13, // AArch64 alias
611 EC_SVC_64 = 0x15,
612 EC_HVC_64 = 0x16,
613 EC_SMC_64 = 0x17,
614 EC_TRAPPED_MSR_MRS_64 = 0x18,
615 EC_PREFETCH_ABORT_TO_HYP = 0x20,
616 EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias
617 EC_PREFETCH_ABORT_FROM_HYP = 0x21,
618 EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias
619 EC_PC_ALIGNMENT = 0x22,
620 EC_DATA_ABORT_TO_HYP = 0x24,
621 EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias
622 EC_DATA_ABORT_FROM_HYP = 0x25,
623 EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias
624 EC_STACK_PTR_ALIGNMENT = 0x26,
625 EC_FP_EXCEPTION = 0x28,
626 EC_FP_EXCEPTION_64 = 0x2C,
627 EC_SERROR = 0x2F
628 };
629
630 /**
631 * Instruction decoder fault codes in ExtMachInst.
632 */
633 enum DecoderFault : std::uint8_t {
634 OK = 0x0, ///< No fault
635 UNALIGNED = 0x1, ///< Unaligned instruction fault
636
637 PANIC = 0x3, ///< Internal gem5 error
638 };
639
640 BitUnion8(OperatingMode64)
641 Bitfield<0> spX;
642 Bitfield<3, 2> el;
643 Bitfield<4> width;
644 EndBitUnion(OperatingMode64)
645
646 static bool inline
647 opModeIs64(OperatingMode mode)
648 {
649 return ((OperatingMode64)(uint8_t)mode).width == 0;
650 }
651
652 static bool inline
653 opModeIsH(OperatingMode mode)
654 {
655 return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H);
656 }
657
658 static bool inline
659 opModeIsT(OperatingMode mode)
660 {
661 return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T ||
662 mode == MODE_EL3T);
663 }
664
665 static ExceptionLevel inline
666 opModeToEL(OperatingMode mode)
667 {
668 bool aarch32 = ((mode >> 4) & 1) ? true : false;
669 if (aarch32) {
670 switch (mode) {
671 case MODE_USER:
672 return EL0;
673 case MODE_FIQ:
674 case MODE_IRQ:
675 case MODE_SVC:
676 case MODE_ABORT:
677 case MODE_UNDEFINED:
678 case MODE_SYSTEM:
679 return EL1;
680 case MODE_HYP:
681 return EL2;
682 case MODE_MON:
683 return EL3;
684 default:
685 panic("Invalid operating mode: %d", mode);
686 break;
687 }
688 } else {
689 // aarch64
690 return (ExceptionLevel) ((mode >> 2) & 3);
691 }
692 }
693
694 static inline bool
695 badMode(OperatingMode mode)
696 {
697 switch (mode) {
698 case MODE_EL0T:
699 case MODE_EL1T:
700 case MODE_EL1H:
701 case MODE_EL2T:
702 case MODE_EL2H:
703 case MODE_EL3T:
704 case MODE_EL3H:
705 case MODE_USER:
706 case MODE_FIQ:
707 case MODE_IRQ:
708 case MODE_SVC:
709 case MODE_MON:
710 case MODE_ABORT:
711 case MODE_HYP:
712 case MODE_UNDEFINED:
713 case MODE_SYSTEM:
714 return false;
715 default:
716 return true;
717 }
718 }
719
720
721 static inline bool
722 badMode32(OperatingMode mode)
723 {
724 switch (mode) {
725 case MODE_USER:
726 case MODE_FIQ:
727 case MODE_IRQ:
728 case MODE_SVC:
729 case MODE_MON:
730 case MODE_ABORT:
731 case MODE_HYP:
732 case MODE_UNDEFINED:
733 case MODE_SYSTEM:
734 return false;
735 default:
736 return true;
737 }
738 }
739
740} // namespace ArmISA
741
|
743__hash_namespace_begin
| 742namespace std {
|
744
745template<>
746struct hash<ArmISA::ExtMachInst> :
747 public hash<ArmISA::ExtMachInst::__DataType> {
748
749 size_t operator()(const ArmISA::ExtMachInst &emi) const {
750 return hash<ArmISA::ExtMachInst::__DataType>::operator()(emi);
751 }
752
753};
754
| 743
744template<>
745struct hash<ArmISA::ExtMachInst> :
746 public hash<ArmISA::ExtMachInst::__DataType> {
747
748 size_t operator()(const ArmISA::ExtMachInst &emi) const {
749 return hash<ArmISA::ExtMachInst::__DataType>::operator()(emi);
750 }
751
752};
753
|
755__hash_namespace_end
| 754}
|
756
757#endif
| 755
756#endif
|