1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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77
78 // FPSCR fields
79 Bitfield<41, 40> fpscrStride;
80 Bitfield<39, 37> fpscrLen;
81
82 // Bitfields to select mode.
83 Bitfield<36> thumb;
84 Bitfield<35> bigThumb;
85
86 // Made up bitfields that make life easier.
87 Bitfield<33> sevenAndFour;
88 Bitfield<32> isMisc;
89
90 uint32_t instBits;
91
92 // All the different types of opcode fields.

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138
139 Bitfield<11, 0> immed11_0;
140 Bitfield<7, 0> immed7_0;
141
142 Bitfield<11, 8> immedHi11_8;
143 Bitfield<3, 0> immedLo3_0;
144
145 Bitfield<15, 0> regList;
146
147 Bitfield<23, 0> offset;
148
149 Bitfield<23, 0> immed23_0;
150
151 Bitfield<11, 8> cpNum;
152 Bitfield<18, 16> fn;
153 Bitfield<14, 12> fd;
154 Bitfield<3> fpRegImm;
155 Bitfield<3, 0> fm;
156 Bitfield<2, 0> fpImm;

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208 class PCState : public GenericISA::UPCState<MachInst>
209 {
210 protected:
211
212 typedef GenericISA::UPCState<MachInst> Base;
213
214 enum FlagBits {
215 ThumbBit = (1 << 0),
216 JazelleBit = (1 << 1)
217 };
218 uint8_t flags;
219 uint8_t nextFlags;
220 uint8_t _itstate;
221 uint8_t _nextItstate;
222 uint8_t _size;
223 public:
224 PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0)

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299 nextJazelle(bool val)
300 {
301 if (val)
302 nextFlags |= JazelleBit;
303 else
304 nextFlags &= ~JazelleBit;
305 }
306
307 uint8_t
308 itstate() const
309 {
310 return _itstate;
311 }
312
313 void
314 itstate(uint8_t value)

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369
370 Addr
371 instPC() const
372 {
373 return pc() + (thumb() ? 4 : 8);
374 }
375
376 void
377 instNPC(uint32_t val)
378 {
379 npc(val &~ mask(nextThumb() ? 1 : 2));
380 }
381
382 Addr
383 instNPC() const
384 {
385 return npc();
386 }
387
388 // Perform an interworking branch.
389 void
390 instIWNPC(uint32_t val)
391 {
392 bool thumbEE = (thumb() && jazelle());
393
394 Addr newPC = val;
395 if (thumbEE) {
396 if (bits(newPC, 0)) {
397 newPC = newPC & ~mask(1);
398 } // else we have a bad interworking address; do not call

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412 }
413 }
414 npc(newPC);
415 }
416
417 // Perform an interworking branch in ARM mode, a regular branch
418 // otherwise.
419 void
420 instAIWNPC(uint32_t val)
421 {
422 if (!thumb() && !jazelle())
423 instIWNPC(val);
424 else
425 instNPC(val);
426 }
427
428 bool

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465 // Shift types for ARM instructions
466 enum ArmShiftType {
467 LSL = 0,
468 LSR,
469 ASR,
470 ROR
471 };
472
473 typedef uint64_t LargestRead;
474 // Need to use 64 bits to make sure that read requests get handled properly
475
476 typedef int RegContextParam;
477 typedef int RegContextVal;
478
479 //used in FP convert & round function
480 enum ConvertType{

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503 //used in FP convert & round function
504 enum RoundMode{
505 RND_ZERO,
506 RND_DOWN,
507 RND_UP,
508 RND_NEAREST
509 };
510
511 enum OperatingMode {
512 MODE_USER = 16,
513 MODE_FIQ = 17,
514 MODE_IRQ = 18,
515 MODE_SVC = 19,
516 MODE_MON = 22,
517 MODE_ABORT = 23,
518 MODE_UNDEFINED = 27,
519 MODE_SYSTEM = 31,
520 MODE_MAXMODE = MODE_SYSTEM
521 };
522
523 static inline bool
524 badMode(OperatingMode mode)
525 {
526 switch (mode) {
527 case MODE_USER:
528 case MODE_FIQ:
529 case MODE_IRQ:
530 case MODE_SVC:
531 case MODE_MON:
532 case MODE_ABORT:
533 case MODE_UNDEFINED:
534 case MODE_SYSTEM:
535 return false;
536 default:
537 return true;
538 }
539 }
540
541} // namespace ArmISA
542
543__hash_namespace_begin
544 template<>
545 struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
546 size_t operator()(const ArmISA::ExtMachInst &emi) const {
547 return hash<uint32_t>::operator()((uint32_t)emi);
548 };
549 };
550__hash_namespace_end
551
552#endif