1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_TYPES_HH__
44#define __ARCH_ARM_TYPES_HH__
45
46#include "arch/generic/types.hh"
47#include "base/bitunion.hh"
48#include "base/hashmap.hh"
49#include "base/misc.hh"
50#include "base/types.hh"
51#include "debug/Decoder.hh"
52
53namespace ArmISA
54{
55 typedef uint32_t MachInst;
56

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478
479 bool
480 operator != (const PCState &opc) const
481 {
482 return !(*this == opc);
483 }
484
485 void
486 serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
487 {
488 Base::serialize(cp);
489 SERIALIZE_SCALAR(flags);
490 SERIALIZE_SCALAR(_size);
491 SERIALIZE_SCALAR(nextFlags);
492 SERIALIZE_SCALAR(_itstate);
493 SERIALIZE_SCALAR(_nextItstate);
494 }
495
496 void
497 unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
498 {
499 Base::unserialize(cp);
500 UNSERIALIZE_SCALAR(flags);
501 UNSERIALIZE_SCALAR(_size);
502 UNSERIALIZE_SCALAR(nextFlags);
503 UNSERIALIZE_SCALAR(_itstate);
504 UNSERIALIZE_SCALAR(_nextItstate);
505 }

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735 return false;
736 default:
737 return true;
738 }
739 }
740
741} // namespace ArmISA
742
743__hash_namespace_begin
744
745template<>
746struct hash<ArmISA::ExtMachInst> :
747 public hash<ArmISA::ExtMachInst::__DataType> {
748
749 size_t operator()(const ArmISA::ExtMachInst &emi) const {
750 return hash<ArmISA::ExtMachInst::__DataType>::operator()(emi);
751 }
752
753};
754
755__hash_namespace_end
756
757#endif