| tarmac_parser.cc (13116:d3c3e2533928) | tarmac_parser.cc (13611:c8b7847b4171) |
|---|---|
| 1/* 2 * Copyright (c) 2011,2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 633 unchanged lines hidden (view full) --- 642 for (; it != end; ++it) { 643 switch (it->type) { 644 case REG_R: 645 case REG_X: 646 value_lo = thread->readIntReg(it->index); 647 break; 648 case REG_S: 649 if (instRecord.isetstate == ISET_A64) | 1/* 2 * Copyright (c) 2011,2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 633 unchanged lines hidden (view full) --- 642 for (; it != end; ++it) { 643 switch (it->type) { 644 case REG_R: 645 case REG_X: 646 value_lo = thread->readIntReg(it->index); 647 break; 648 case REG_S: 649 if (instRecord.isetstate == ISET_A64) |
| 650 value_lo = thread->readFloatRegBits(it->index * 4); | 650 value_lo = thread->readFloatReg(it->index * 4); |
| 651 else | 651 else |
| 652 value_lo = thread->readFloatRegBits(it->index); | 652 value_lo = thread->readFloatReg(it->index); |
| 653 break; 654 case REG_D: 655 if (instRecord.isetstate == ISET_A64) | 653 break; 654 case REG_D: 655 if (instRecord.isetstate == ISET_A64) |
| 656 value_lo = thread->readFloatRegBits(it->index * 4) | 657 (uint64_t) thread->readFloatRegBits(it->index * 4 + 1) << | 656 value_lo = thread->readFloatReg(it->index * 4) | 657 (uint64_t) thread->readFloatReg(it->index * 4 + 1) << |
| 658 32; 659 else | 658 32; 659 else |
| 660 value_lo = thread->readFloatRegBits(it->index * 2) | 661 (uint64_t) thread->readFloatRegBits(it->index * 2 + 1) << | 660 value_lo = thread->readFloatReg(it->index * 2) | 661 (uint64_t) thread->readFloatReg(it->index * 2 + 1) << |
| 662 32; 663 break; 664 case REG_Q: 665 check_value_hi = true; 666 if (instRecord.isetstate == ISET_A64) { | 662 32; 663 break; 664 case REG_Q: 665 check_value_hi = true; 666 if (instRecord.isetstate == ISET_A64) { |
| 667 value_lo = thread->readFloatRegBits(it->index * 4) | 668 (uint64_t) thread->readFloatRegBits(it->index * 4 + 1) << | 667 value_lo = thread->readFloatReg(it->index * 4) | 668 (uint64_t) thread->readFloatReg(it->index * 4 + 1) << |
| 669 32; | 669 32; |
| 670 value_hi = thread->readFloatRegBits(it->index * 4 + 2) | 671 (uint64_t) thread->readFloatRegBits(it->index * 4 + 3) << | 670 value_hi = thread->readFloatReg(it->index * 4 + 2) | 671 (uint64_t) thread->readFloatReg(it->index * 4 + 3) << |
| 672 32; 673 } else { | 672 32; 673 } else { |
| 674 value_lo = thread->readFloatRegBits(it->index * 2) | 675 (uint64_t) thread->readFloatRegBits(it->index * 2 + 1) << | 674 value_lo = thread->readFloatReg(it->index * 2) | 675 (uint64_t) thread->readFloatReg(it->index * 2 + 1) << |
| 676 32; | 676 32; |
| 677 value_hi = thread->readFloatRegBits(it->index * 2 + 2) | 678 (uint64_t) thread->readFloatRegBits(it->index * 2 + 3) << | 677 value_hi = thread->readFloatReg(it->index * 2 + 2) | 678 (uint64_t) thread->readFloatReg(it->index * 2 + 3) << |
| 679 32; 680 } 681 break; 682 case REG_MISC: 683 if (it->index == MISCREG_CPSR) { 684 // Read condition codes from aliased integer regs 685 CPSR cpsr = thread->readMiscRegNoEffect(it->index); 686 cpsr.nz = thread->readCCReg(CCREG_NZ); --- 452 unchanged lines hidden --- | 679 32; 680 } 681 break; 682 case REG_MISC: 683 if (it->index == MISCREG_CPSR) { 684 // Read condition codes from aliased integer regs 685 CPSR cpsr = thread->readMiscRegNoEffect(it->index); 686 cpsr.nz = thread->readCCReg(CCREG_NZ); --- 452 unchanged lines hidden --- |