tlb.hh (9738:304a37519d11) tlb.hh (10037:5cac77888310)
1/*
1/*
2 * Copyright (c) 2010-2012 ARM Limited
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_TLB_HH__
44#define __ARCH_ARM_TLB_HH__
45
46#include <map>
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/pagetable.hh"
50#include "arch/arm/utility.hh"
51#include "arch/arm/vtophys.hh"
52#include "base/statistics.hh"
46
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/pagetable.hh"
49#include "arch/arm/utility.hh"
50#include "arch/arm/vtophys.hh"
51#include "base/statistics.hh"
52#include "dev/dma_device.hh"
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/fault_fwd.hh"
56#include "sim/tlb.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TableWalker;
53#include "mem/request.hh"
54#include "params/ArmTLB.hh"
55#include "sim/fault_fwd.hh"
56#include "sim/tlb.hh"
57
58class ThreadContext;
59
60namespace ArmISA {
61
62class TableWalker;
63class Stage2LookUp;
64class Stage2MMU;
63
64class TLB : public BaseTLB
65{
66 public:
67 enum ArmFlags {
65
66class TLB : public BaseTLB
67{
68 public:
69 enum ArmFlags {
68 AlignmentMask = 0x1f,
70 AlignmentMask = 0x7,
69
70 AlignByte = 0x0,
71 AlignHalfWord = 0x1,
71
72 AlignByte = 0x0,
73 AlignHalfWord = 0x1,
72 AlignWord = 0x3,
73 AlignDoubleWord = 0x7,
74 AlignQuadWord = 0xf,
75 AlignOctWord = 0x1f,
74 AlignWord = 0x2,
75 AlignDoubleWord = 0x3,
76 AlignQuadWord = 0x4,
77 AlignOctWord = 0x5,
76
78
77 AllowUnaligned = 0x20,
79 AllowUnaligned = 0x8,
78 // Priv code operating as if it wasn't
80 // Priv code operating as if it wasn't
79 UserMode = 0x40,
81 UserMode = 0x10,
80 // Because zero otherwise looks like a valid setting and may be used
81 // accidentally, this bit must be non-zero to show it was used on
82 // purpose.
82 // Because zero otherwise looks like a valid setting and may be used
83 // accidentally, this bit must be non-zero to show it was used on
84 // purpose.
83 MustBeOne = 0x80
85 MustBeOne = 0x40
84 };
86 };
87
88 enum ArmTranslationType {
89 NormalTran = 0,
90 S1CTran = 0x1,
91 HypMode = 0x2,
92 // Secure code operating as if it wasn't (required by some Address
93 // Translate operations)
94 S1S2NsTran = 0x4
95 };
85 protected:
96 protected:
97 TlbEntry* table; // the Page Table
98 int size; // TLB Size
99 bool isStage2; // Indicates this TLB is part of the second stage MMU
100 bool stage2Req; // Indicates whether a stage 2 lookup is also required
101 uint64_t _attr; // Memory attributes for last accessed TLB entry
102 bool directToStage2; // Indicates whether all translation requests should
103 // be routed directly to the stage 2 TLB
86
104
87 TlbEntry *table; // the Page Table
88 int size; // TLB Size
89
90 uint32_t _attr; // Memory attributes for last accessed TLB entry
91
92 TableWalker *tableWalker;
105 TableWalker *tableWalker;
106 TLB *stage2Tlb;
107 Stage2MMU *stage2Mmu;
93
94 // Access Stats
95 mutable Stats::Scalar instHits;
96 mutable Stats::Scalar instMisses;
97 mutable Stats::Scalar readHits;
98 mutable Stats::Scalar readMisses;
99 mutable Stats::Scalar writeHits;
100 mutable Stats::Scalar writeMisses;

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116 Stats::Formula misses;
117 Stats::Formula accesses;
118
119 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
120
121 bool bootUncacheability;
122
123 public:
108
109 // Access Stats
110 mutable Stats::Scalar instHits;
111 mutable Stats::Scalar instMisses;
112 mutable Stats::Scalar readHits;
113 mutable Stats::Scalar readMisses;
114 mutable Stats::Scalar writeHits;
115 mutable Stats::Scalar writeMisses;

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131 Stats::Formula misses;
132 Stats::Formula accesses;
133
134 int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
135
136 bool bootUncacheability;
137
138 public:
124 typedef ArmTLBParams Params;
125 TLB(const Params *p);
139 TLB(const ArmTLBParams *p);
140 TLB(const Params *p, int _size, TableWalker *_walker);
126
127 /** Lookup an entry in the TLB
128 * @param vpn virtual address
129 * @param asn context id/address space id to use
141
142 /** Lookup an entry in the TLB
143 * @param vpn virtual address
144 * @param asn context id/address space id to use
145 * @param vmid The virtual machine ID used for stage 2 translation
146 * @param secure if the lookup is secure
147 * @param hyp if the lookup is done from hyp mode
130 * @param functional if the lookup should modify state
148 * @param functional if the lookup should modify state
131 * @return pointer to TLB entrry if it exists
149 * @param ignore_asn if on lookup asn should be ignored
150 * @return pointer to TLB entry if it exists
132 */
151 */
133 TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
152 TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
153 bool secure, bool functional,
154 bool ignore_asn, uint8_t target_el);
134
135 virtual ~TLB();
155
156 virtual ~TLB();
157
158 /// setup all the back pointers
159 virtual void init();
160
161 void setMMU(Stage2MMU *m);
162
136 int getsize() const { return size; }
137
138 void insert(Addr vaddr, TlbEntry &pte);
139
163 int getsize() const { return size; }
164
165 void insert(Addr vaddr, TlbEntry &pte);
166
140 /** Reset the entire TLB */
141 void flushAll();
167 Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
168 Translation *translation, bool timing, bool functional,
169 bool is_secure, ArmTranslationType tranType);
142
170
171 Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
172 Mode mode, Translation *translation, bool timing,
173 bool functional, TlbEntry *mergeTe);
174
175 Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
176 Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
177 ThreadContext *tc);
178
179
180 /** Reset the entire TLB
181 * @param secure_lookup if the operation affects the secure world
182 */
183 void flushAllSecurity(bool secure_lookup, uint8_t target_el,
184 bool ignore_el = false);
185
186 /** Remove all entries in the non secure world, depending on whether they
187 * were allocated in hyp mode or not
188 * @param hyp if the opperation affects hyp mode
189 */
190 void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
191
192
193 /** Reset the entire TLB. Used for CPU switching to prevent stale
194 * translations after multiple switches
195 */
196 void flushAll()
197 {
198 flushAllSecurity(false, 0, true);
199 flushAllSecurity(true, 0, true);
200 }
201
143 /** Remove any entries that match both a va and asn
144 * @param mva virtual address to flush
145 * @param asn contextid/asn to flush on match
202 /** Remove any entries that match both a va and asn
203 * @param mva virtual address to flush
204 * @param asn contextid/asn to flush on match
205 * @param secure_lookup if the operation affects the secure world
146 */
206 */
147 void flushMvaAsid(Addr mva, uint64_t asn);
207 void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
208 uint8_t target_el);
148
149 /** Remove any entries that match the asn
150 * @param asn contextid/asn to flush on match
209
210 /** Remove any entries that match the asn
211 * @param asn contextid/asn to flush on match
212 * @param secure_lookup if the operation affects the secure world
151 */
213 */
152 void flushAsid(uint64_t asn);
214 void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
153
154 /** Remove all entries that match the va regardless of asn
155 * @param mva address to flush from cache
215
216 /** Remove all entries that match the va regardless of asn
217 * @param mva address to flush from cache
218 * @param secure_lookup if the operation affects the secure world
219 * @param hyp if the operation affects hyp mode
156 */
220 */
157 void flushMva(Addr mva);
221 void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
158
222
159 Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
160 Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
161 bool is_write, uint8_t domain, bool sNp);
223 Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain);
224 Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec,
225 bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level);
162
226
163 void printTlb();
227 void printTlb() const;
164
165 void allCpusCaching() { bootUncacheability = true; }
166 void demapPage(Addr vaddr, uint64_t asn)
167 {
228
229 void allCpusCaching() { bootUncacheability = true; }
230 void demapPage(Addr vaddr, uint64_t asn)
231 {
168 flushMvaAsid(vaddr, asn);
232 // needed for x86 only
233 panic("demapPage() is not implemented.\n");
169 }
170
171 static bool validVirtualAddress(Addr vaddr);
172
173 /**
174 * Do a functional lookup on the TLB (for debugging)
175 * and don't modify any internal state
176 * @param tc thread context to get the context id from
177 * @param vaddr virtual address to translate
178 * @param pa returned physical address
179 * @return if the translation was successful
180 */
181 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
182
183 /**
184 * Do a functional lookup on the TLB (for checker cpu) that
185 * behaves like a normal lookup without modifying any page table state.
186 */
234 }
235
236 static bool validVirtualAddress(Addr vaddr);
237
238 /**
239 * Do a functional lookup on the TLB (for debugging)
240 * and don't modify any internal state
241 * @param tc thread context to get the context id from
242 * @param vaddr virtual address to translate
243 * @param pa returned physical address
244 * @return if the translation was successful
245 */
246 bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
247
248 /**
249 * Do a functional lookup on the TLB (for checker cpu) that
250 * behaves like a normal lookup without modifying any page table state.
251 */
187 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
252 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
253 ArmTranslationType tranType = NormalTran);
188
189 /** Accessor functions for memory attributes for last accessed TLB entry
190 */
191 void
254
255 /** Accessor functions for memory attributes for last accessed TLB entry
256 */
257 void
192 setAttr(uint32_t attr)
258 setAttr(uint64_t attr)
193 {
194 _attr = attr;
195 }
259 {
260 _attr = attr;
261 }
196 uint32_t
262
263 uint64_t
197 getAttr() const
198 {
199 return _attr;
200 }
201
202 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
203 Translation *translation, bool &delay,
264 getAttr() const
265 {
266 return _attr;
267 }
268
269 Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
270 Translation *translation, bool &delay,
204 bool timing, bool functional = false);
271 bool timing, ArmTranslationType tranType, bool functional = false);
205 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
206 Translation *translation, bool &delay, bool timing);
272 Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
273 Translation *translation, bool &delay, bool timing);
207 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
274 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
275 ArmTranslationType tranType = NormalTran);
208 Fault translateTiming(RequestPtr req, ThreadContext *tc,
276 Fault translateTiming(RequestPtr req, ThreadContext *tc,
209 Translation *translation, Mode mode);
277 Translation *translation, Mode mode,
278 ArmTranslationType tranType = NormalTran);
279 Fault translateComplete(RequestPtr req, ThreadContext *tc,
280 Translation *translation, Mode mode, ArmTranslationType tranType,
281 bool callFromS2);
210 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
211
212 void drainResume();
213
214 // Checkpointing
215 void serialize(std::ostream &os);
216 void unserialize(Checkpoint *cp, const std::string &section);
217

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224 * returned, hence the use of a pointer rather than a
225 * reference. For ARM this method will always return a valid port
226 * pointer.
227 *
228 * @return A pointer to the walker master port
229 */
230 virtual BaseMasterPort* getMasterPort();
231
282 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
283
284 void drainResume();
285
286 // Checkpointing
287 void serialize(std::ostream &os);
288 void unserialize(Checkpoint *cp, const std::string &section);
289

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296 * returned, hence the use of a pointer rather than a
297 * reference. For ARM this method will always return a valid port
298 * pointer.
299 *
300 * @return A pointer to the walker master port
301 */
302 virtual BaseMasterPort* getMasterPort();
303
304 /**
305 * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
306 * access the table walker port of this TLB so that it can
307 * orchestrate staged translations.
308 *
309 * @return The table walker DMA port
310 */
311 DmaPort& getWalkerPort();
312
232 // Caching misc register values here.
233 // Writing to misc registers needs to invalidate them.
234 // translateFunctional/translateSe/translateFs checks if they are
235 // invalid and call updateMiscReg if necessary.
236protected:
313 // Caching misc register values here.
314 // Writing to misc registers needs to invalidate them.
315 // translateFunctional/translateSe/translateFs checks if they are
316 // invalid and call updateMiscReg if necessary.
317protected:
318 bool aarch64;
319 ExceptionLevel aarch64EL;
237 SCTLR sctlr;
320 SCTLR sctlr;
321 SCR scr;
238 bool isPriv;
322 bool isPriv;
239 CONTEXTIDR contextId;
323 bool isSecure;
324 bool isHyp;
325 TTBCR ttbcr;
326 uint16_t asid;
327 uint8_t vmid;
240 PRRR prrr;
241 NMRR nmrr;
328 PRRR prrr;
329 NMRR nmrr;
330 HCR hcr;
242 uint32_t dacr;
243 bool miscRegValid;
331 uint32_t dacr;
332 bool miscRegValid;
244 void updateMiscReg(ThreadContext *tc)
245 {
246 sctlr = tc->readMiscReg(MISCREG_SCTLR);
247 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
248 isPriv = cpsr.mode != MODE_USER;
249 contextId = tc->readMiscReg(MISCREG_CONTEXTIDR);
250 prrr = tc->readMiscReg(MISCREG_PRRR);
251 nmrr = tc->readMiscReg(MISCREG_NMRR);
252 dacr = tc->readMiscReg(MISCREG_DACR);
253 miscRegValid = true;
254 }
333 ArmTranslationType curTranType;
334
335 // Cached copies of system-level properties
336 bool haveLPAE;
337 bool haveVirtualization;
338 bool haveLargeAsid64;
339
340 void updateMiscReg(ThreadContext *tc,
341 ArmTranslationType tranType = NormalTran);
342
255public:
256 const Params *
257 params() const
258 {
259 return dynamic_cast<const Params *>(_params);
260 }
261 inline void invalidateMiscReg() { miscRegValid = false; }
343public:
344 const Params *
345 params() const
346 {
347 return dynamic_cast<const Params *>(_params);
348 }
349 inline void invalidateMiscReg() { miscRegValid = false; }
350
351private:
352 /** Remove any entries that match both a va and asn
353 * @param mva virtual address to flush
354 * @param asn contextid/asn to flush on match
355 * @param secure_lookup if the operation affects the secure world
356 * @param hyp if the operation affects hyp mode
357 * @param ignore_asn if the flush should ignore the asn
358 */
359 void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
360 bool hyp, bool ignore_asn, uint8_t target_el);
361
362 bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
262};
263
264} // namespace ArmISA
265
266#endif // __ARCH_ARM_TLB_HH__
363};
364
365} // namespace ArmISA
366
367#endif // __ARCH_ARM_TLB_HH__