tlb.hh (8527:6bac5b04d588) tlb.hh (8552:f51e3dce9521)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 208 unchanged lines hidden (view full) ---

217
218 // Caching misc register values here.
219 // Writing to misc registers needs to invalidate them.
220 // translateFunctional/translateSe/translateFs checks if they are
221 // invalid and call updateMiscReg if necessary.
222protected:
223 SCTLR sctlr;
224 bool isPriv;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 208 unchanged lines hidden (view full) ---

217
218 // Caching misc register values here.
219 // Writing to misc registers needs to invalidate them.
220 // translateFunctional/translateSe/translateFs checks if they are
221 // invalid and call updateMiscReg if necessary.
222protected:
223 SCTLR sctlr;
224 bool isPriv;
225 uint32_t contextId;
225 CONTEXTIDR contextId;
226 PRRR prrr;
227 NMRR nmrr;
228 uint32_t dacr;
229 bool miscRegValid;
230 void updateMiscReg(ThreadContext *tc)
231 {
232 sctlr = tc->readMiscReg(MISCREG_SCTLR);
233 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);

--- 19 unchanged lines hidden --- 		226 PRRR prrr;
227 NMRR nmrr;
228 uint32_t dacr;
229 bool miscRegValid;
230 void updateMiscReg(ThreadContext *tc)
231 {
232 sctlr = tc->readMiscReg(MISCREG_SCTLR);
233 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);

--- 19 unchanged lines hidden ---