tlb.hh (7749:859e8bc1cdc2) tlb.hh (7781:a9f9eed35b18)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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204 Translation *translation, Mode mode);
205
206 // Checkpointing
207 void serialize(std::ostream &os);
208 void unserialize(Checkpoint *cp, const std::string &section);
209
210 void regStats();
211
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 195 unchanged lines hidden (view full) ---

204 Translation *translation, Mode mode);
205
206 // Checkpointing
207 void serialize(std::ostream &os);
208 void unserialize(Checkpoint *cp, const std::string &section);
209
210 void regStats();
211
212 // Get the port from the table walker and return it
213 virtual Port *getPort();
214
212 // Caching misc register values here.
213 // Writing to misc registers needs to invalidate them.
214 // translateFunctional/translateSe/translateFs checks if they are
215 // invalid and call updateMiscReg if necessary.
216protected:
217 SCTLR sctlr;
218 bool isPriv;
219 uint32_t contextId;

--- 22 unchanged lines hidden --- 		215 // Caching misc register values here.
216 // Writing to misc registers needs to invalidate them.
217 // translateFunctional/translateSe/translateFs checks if they are
218 // invalid and call updateMiscReg if necessary.
219protected:
220 SCTLR sctlr;
221 bool isPriv;
222 uint32_t contextId;

--- 22 unchanged lines hidden ---